General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER" />
參數(shù)資料
型號(hào)： XR16L784IV-F
廠商： Exar Corporation
文件頁數(shù)： 15/51頁
文件大?。?/td> 0K
描述： IC UART 8B 3.3V QUAD 64LQFP
標(biāo)準(zhǔn)包裝： 160
特點(diǎn)： *
通道數(shù)： 4，QUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
其它名稱： 1016-1282
XR16L784
22
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
3.1.2
General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for a periodic event. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
TABLE 9: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY
BIT2 BIT1 BIT0
INTERRUPT SOURCE(S) AND CLEARING
x
0
None
1
0
1
RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the
RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR
register.
2
0
1
0
RXRDY Time-out: Cleared when the FIFO becomes empty.
3
0
1
TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1
0
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clear after reading MSR register; Xoff/Xon or special char. detect INT clears after reading
ISR register.
5
1
0
1
Reserved.
6
1
0
Reserved.
7
1
TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL regis-
ter. Reserved in other channels.
FIGURE 15. TIMER/COUNTER CIRCUIT.
TABLE 10: TIMER CONTROL REGISTER
TIMERCNTL [0]
Logic 0 (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1]
Logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2]
Logic0 (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3]
Logic 0 (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [7:4]
Reserved (defaults to zero).
TMRCK
OSC. CLOCK
TIMERCNTL [3]
16-Bit
Timer/Counter
TIMERCNTL [2]
Re-trigger
Single-shot
TIMERCNTL [1]
Start/Stop
TIMERCNTL [0]
Timer Interrupt, Ch-0 INT=7
Time-out
Timer Interrupt Enable
Single/Re-triggerable
TIMERMSB and TIMERLSB
(16-bit Value)
0
1
0
1
0
1
No Interrupt
Clock
Select
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