參數(shù)資料
型號(hào)： XR16L651IM-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 5/56頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 32B 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 32 字節(jié)
規(guī)程： 打印機(jī)，RS232，RS422，RS485
電源電壓： 2.25 V ~ 5.5 V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
á
XR16L651
REV. 1.3.0
2.25V TO 5.5V UART WITH 32-BYTE FIFO
13
2.7
Crystal Oscillator or External Clock
The 651 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock buffer input
with XTAL2 pin being the output. Caution if external clock is used: XTAL1 input is not 5 Volt tolerant. For
programming details, see “Programmable Baud Rate Generator.”
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typically, the oscillator connections are shown in Figure 7. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
2.8
Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter. The prescaler is
controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides
this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data
rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The
BRG divisor (DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the
BRG must be programmed during initialization to the operating data rate.
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500 Κ1Μ
XTAL1
XTAL2
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