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Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XR16L651
2.25V TO 5.5V UART WITH 32-BYTE FIFO
JANUARY 2004
REV. 1.3.0
GENERAL DESCRIPTION
The XR16L6511 (651) is a 2.25 to 5.5 volt Universal
Asynchronous Receiver and Transmitter (UART) with
5 volt tolerant inputs. This device supports Intel and
Motorola
data
bus
interfaces
and
is
software
compatible to industry standard 16C450, 16C550,
ST16C580 and ST16C650A UARTs.
The 651 has 32 bytes of TX and RX FIFOs and is
capable of operating up to serial data rates of 3.125
Mbps at 5 volt supply voltage. The internal registers
include the 16C550 register set plus Exar’s enhanced
registers for additional features to support today’s
highly demanding data communication needs. The
enhanced features include automatic hardware and
software flow control, selectable TX and RX trigger
levels, and wireless infrared (IrDA) encoder/decoder.
The device provides a new capability to give user the
ability to program the wireless infrared encoder
output pulse width, hence reducing the power
consumption of a handheld unit.
The XR16L651 device comes in a small 7x7x1mm
48-pin TQFP package in both the commercial and
industrial temperature ranges.
NOTE: 1 Covered by US patents #5,649,122.
FEATURES
Added feature in devices with top mark date code of
"C2 YYWW" and newer:
s
0 ns address hold time
2.25 to 5.5 Volt Operation w/ 5 Volt Tolerant Inputs
ST16C450/550/580/650A Software Compatible
Intel, Motorola or PC Mode 8-bit Bus Interface
Up to 3.125 Mbps Data Rate at 5 Volt Operation
32-byte Transmit and Receive FIFOs
Automatic RS485 Half-Duplex Control Output
Automatic Hardware (RTS/CTS) Flow Control
Hardware Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Infrared (IrDA) Encoder/Decoder Enable Input
Programmable Infrared Encoder Pulse Width
Sleep Mode with Wake-up Indicator via interrupt
APPLICATIONS
Battery Operated Electronics
Internet Appliances
Handheld Terminal
Personal Digital Assistants
Cellular Phones DataPort
Wireless Infrared Data Communications Systems
FIGURE 1. BLOCK DIAGRAM
XTAL1/CLK
XTAL2
Crystal Osc/Buffer
DTR#, DSR#,
RTS#, CTS#,
CD#, RI#
Intel,
Motorola
or PC
Data Bus
Interface
32 Byte TX FIFO
Baud Rate Generator
Infrared Encoder and
Pulse Width Control
Transmitter
UART
Configuration
Regs
IOR
IOR#
32 Byte RX FIFO
Infrared
Decoder
Receiver with Auto
Software Flow Control
Modem Control Signals
TX
RX
CTS Flow
Control
RTS Flow
Control
BRG
Prescaler
CS1
CS0
DDIS#
INT
TXRDY#
RDRDY#
A2:A0
D7:D0
IOW
CS2#
IM#
PCMODE#
S1
S2
S3
IRQA
IRQB
IRQC
IOW#/R/W#
RESET
PC Mode:
COM 1 to 4
Decode Logic
ENIR