TABLE 10: SOFTWARE F
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� XR16L580IMTR-F
寤犲晢锛� Exar Corporation
鏂囦欢闋佹暩(sh霉)锛� 28/49闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC UART FIFO 16B 48TQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,500
鐗归粸锛� *
閫氶亾鏁�(sh霉)锛� 1锛孶ART
FIFO's锛� 16 瀛楃瘈(ji茅)
瑕�(gu墨)绋嬶細 RS232锛孯S422
闆绘簮闆诲锛� 2.25 V ~ 5.5 V
甯惰嚜鍕曟祦閲忔帶鍒跺姛鑳斤細 鏄�
甯禝rDA 绶ㄧ⒓鍣�/瑙g⒓鍣細 鏄�
甯舵晠闅滃暉鍕曚綅妾㈡脯鍔熻兘锛� 鏄�
甯惰(di脿o)鍒惰В瑾�(di脿o)鍣ㄦ帶鍒跺姛鑳斤細 鏄�
甯禖MOS锛� 鏄�
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 48-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-TQFP锛�7x7锛�
鍖呰锛� 甯跺嵎 (TR)
TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
XR16L580
34
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.4.2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= 鈥�10鈥�) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= 鈥�01鈥�) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
XR16L651 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:2.25V TO 5.5V UART WITH 32-BYTE FIFO
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XR16L651CM-0A-EVB 鍔熻兘鎻忚堪:UART 鎺ュ彛闆嗘垚闆昏矾 Supports L651 48 ld TQFP, ISA Interface RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 鏁�(sh霉)鎿�(j霉)閫熺巼:3 Mbps 闆绘簮闆诲-鏈€澶�:3.6 V 闆绘簮闆诲-鏈€灏�:2.7 V 闆绘簮闆绘祦:20 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:LQFP-48 灏佽:Reel
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XR16L651CMTR-F 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 鍒堕€犲晢:Exar Corporation 鍔熻兘鎻忚堪:XR16L651CMTR-F