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參數(shù)資料
| 型號(hào)： | XR16L580IMTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 19/49頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS422 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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XR16L580
26
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
REV. 1.4.2
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
This bit has no functionality in the 24-QFN package.
Logic 0 = Disable the RTS# interrupt (default).
Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
This bit has no functionality in the 24-QFN package.
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by
EFR bit-7.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by
EFR bit-6.
Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
4.5.2
Interrupt Clearing:
LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s)
that generated the interrupt(s) is (are) read from the FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading the RHR register.
TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
MSR interrupt is cleared by reading the MSR register.
Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
Special character interrupt is cleared by reading the ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by reading the MSR register.
Wake-up interrupt is cleared by reading the ISR register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L651 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V UART WITH 32-BYTE FIFO |
| XR16L651CM-0A-EVB | 功能描述:UART 接口集成電路 Supports L651 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CM-F | 功能描述:UART 接口集成電路 UARTW/32BYTEFIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L651CMTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 2.5V/3.3V/5V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16L651CMTR-F |
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