參數(shù)資料
型號(hào): XR16L2752IJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 9/49頁(yè)
文件大小: 619K
代理商: XR16L2752IJ
xr
REV. 1.2.0
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
9
2.9
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 3
and 4
summarize the operating behavior for the transmitter and receiver. Also see
Figures 18
through
23
.
INTA and INTB Outputs
2.10
The 2752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
Crystal Oscillator or External Clock Input
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
Auto RS485
Mode
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1 (FIFO E
NABLED
)
INTA/B Pin
NO
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
INTA/B Pin
YES
LOW = a byte in THR
HIGH = transmitter empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or transmitter empty
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1
(FIFO E
NABLED
)
INTA/B Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500 K
1 M
XTAL1
XTAL2
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