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參數(shù)資料
| 型號(hào)： | XR16L2752IJ |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 13/49頁(yè) |
| 文件大?。?/td> | 619K |
| 代理商： | XR16L2752IJ |
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xr
REV. 1.2.0
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
13
when data is not received for 4 word lengths as defined by LCR[1,0] plus 12 bits time. This is equivalent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.13.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
N
OTE
:
Table-B selected as Trigger Table for
Figure 10
(
Table 10 on page 27
).
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X Clock
(EMSR bit-7)
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Clock
(EMSR bit-7)
E
(
E
L
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO Trigger=16
Example
-:
bytes
(See Note Below)
Data falls to 8
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
Data fills to 24
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
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| XR16L580 | SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L580IL | SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L580IM | SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L2752IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2752IJTR-F | 制造商:Exar Corporation 功能描述:XR16L2752 Series 6.25 Mbps 5.5 V Dual UART With 64-Byte FIFO - PLCC-44 |
| XR16L570 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L570_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L570IL24 | 功能描述:UART 接口集成電路 UART w/ POWER SAVE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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