參數(shù)資料
型號(hào): XR16L2550IL
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, QCC32
封裝: 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
文件頁數(shù): 9/45頁
文件大?。?/td> 278K
代理商: XR16L2550IL
á
REV. 1.0.0
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
9
2.8
The L2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
Crystal Oscillator or External Clock Input
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see
Figure 4
), with an external 500 k
to
1 M
resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in
Figure 4
. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
FCR B
IT
-0 = 0
(FIFO D
ISABLED
)
FCR B
IT
-0 = 1
(FIFO E
NABLED
)
INTA/B Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500 Κ 1 Μ
XTAL1
XTAL2
相關(guān)PDF資料
PDF描述
XR16L2550IM LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IL LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IM LOW VOLTAGE DUART WITH POWERSAVE
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