參數(shù)資料
型號(hào): XR16L2550IL
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: LOW VOLTAGE DUART WITH 16-BYTE FIFO
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, QCC32
封裝: 5 X 5 MM, 0.90 MM HEIGHT, QFN-32
文件頁數(shù): 4/45頁
文件大小: 278K
代理商: XR16L2550IL
XR16L2550
LOW VOLTAGE DUART WITH 16-BYTE FIFO
á
REV. 1.0.0
4
TXRDYB#
-
12
6
O
UART channel B Transmitter Ready (active low). The out-
put provides the TX FIFO/THR status for transmit channel
B. If it is not used, leave it unconnected.
RXRDYB#
-
23
18
O
UART channel B Receiver Ready (active low). This output
provides the RX FIFO/RHR status for receive channel B.
If it is not used, leave it unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
5
13
7
O
UART channel A Transmit Data. If it is not used, leave it
unconnected.
RXA
4
11
5
I
UART channel A Receive Data. Normal receive data input
must idle at logic 1 condition. If it is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
RTSA#
23
36
33
O
UART channel A Request-to-Send (active low) or general
purpose output. This output must be asserted prior to
using auto RTS flow control, see EFR[6], MCR[1] and
IER[6]. If it is not used, leave it unconnected.
CTSA#
25
40
38
I
UART channel A Clear-to-Send (active low) or general
purpose input. It can be used for auto CTS flow control,
see EFR[7] and IER[7]. This input should be connected to
VCC when not used.
DTRA#
-
37
34
O
UART channel A Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRA#
-
41
39
I
UART channel A Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
CDA#
-
42
40
I
UART channel A Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
RIA#
-
43
41
I
UART channel A Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC
when not used. This input has no effect on the UART.
OP2A#
-
35
32
O
Output Port 2 Channel A - The output state is defined by
the user and through the software setting of MCR[3].
INTA is set to the active mode and OP2A# output to a
logic 0 when MCR[3] is set to a logic 1. INTA is set to the
three state mode and OP2A# to a logic 1 when MCR[3] is
set to a logic 0. This output should not be used as a gen-
eral output else it will disturb the INTA output functionality.
If it is not used at all, leave it unconnected.
TXB
6
14
8
O
UART channel B Transmit Data. If it is not used, leave it
unconnected.
RXB
3
10
4
I
UART channel B Receive Data. Normal receive data input
must idle at logic 1 condition. If it is not used, tie it to VCC
or pull it high via a 100k ohm resistor.
Pin Description
N
AME
32-QFN
P
IN
#
44-PLCC
P
IN
#
48-TQFP
P
IN
#
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XR16L2550IM LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2550 LOW VOLTAGE DUART WITH 16-BYTE FIFO
XR16L2551 LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IL LOW VOLTAGE DUART WITH POWERSAVE
XR16L2551IM LOW VOLTAGE DUART WITH POWERSAVE
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