參數(shù)資料
型號(hào)： XQ2V6000-4CF1144M
廠商： XILINX INC
元件分類： FPGA
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： FPGA, 8448 CLBS, 6000000 GATES, 650 MHz, CBGA1144
封裝： 1 MM PITCH, CERAMIC, MS-034-AAR-1, FCGA-1144
文件頁數(shù)： 73/128頁
文件大?。?/td> 2738K
代理商： XQ2V6000-4CF1144M
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
73
R
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for QPro Virtex-II
source-synchronous transmitter and receiver data-valid windows.
Table 68:
Duty Cycle Distortion and Clock-Tree Skew
Description
Symbol
Device
Value
Units
Duty Cycle Distortion
(1)
T
DCD_CLK0
All
140
ps
T
DCD_CLK180
All
50
ps
Clock Tree Skew
(2)
T
CKSKEW
XQ2V1000
90
ps
XQ2V3000
110
ps
XQ2V6000
550
ps
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused
by asymmetrical rise/fall times.
T
DCD_CLK0
applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
T
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
in the I/O.
This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx
FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
2.
Table 69:
Package Skew
Description
Symbol
Device/Package
Value
Units
Package Skew
(1)
T
PKGSKEW
XQ2V6000/CF1144
90
ps
Notes:
1.
These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).
Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.
2.
Table 70:
Sample Window
Description
Symbol
Device
Value
Units
Sampling Error at Receiver Pins
(1)
T
SAMP
XQ2V1000
TBD
ps
XQ2V3000
TBD
ps
XQ2V6000
TBD
ps
Notes:
1.
This parameter indicates the total sampling error of QPro Virtex-II
DDR input registers across voltage, temperature, and process.
The characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 and CLK180 DCM jitter
- Worst-case Duty-Cycle Distortion - T
DCD_CLK180
- DCM accuracy (phase offset)
- DCM phase shift resolution.
These measurements do not include package or clock tree skew.
ds122_1_1.fm Page 73 Wednesday, January 7, 2004 9:15 PM
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