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| 型號(hào)： | XQ2V6000-4CF1144M |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | QPro Virtex-II 1.5V Military QML Platform FPGAs |
| 中文描述： | FPGA, 8448 CLBS, 6000000 GATES, 650 MHz, CBGA1144 |
| 封裝： | 1 MM PITCH, CERAMIC, MS-034-AAR-1, FCGA-1144 |
| 文件頁(yè)數(shù)： | 28/128頁(yè) |
| 文件大?。?/td> | 2738K |
| 代理商： | XQ2V6000-4CF1144M |
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QPro Virtex-II 1.5V Military QML Platform FPGAs
28
www.xilinx.com
1-800-255-7778
DS122 (v1.1) January 7, 2004
Product Specification
R
Table 19
illustrates the different configurations available on
Ports A and B.
If both ports are configured in either 2K x 9-bit, 1K x 18-bit,
or 512 x 36-bit configurations, the 18 Kbit block is accessi-
ble from Port A or B. If both ports are configured in either
16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations, the
16 Kbit block is accessible from Port A or Port B. All other
configurations result in one port having access to an 18 Kbit
memory block and the other port having access to a 16 Kbit
subset of the memory block equal to 16 Kbits.
Each block SelectRAM cell is a fully synchronous memory,
as illustrated in
Figure 31
. The two ports have independent
inputs and outputs and are independently clocked.
Port Aspect Ratios
Table 20
shows the depth and the width aspect ratios for the
18 Kbit block SelectRAM. Virtex-II block SelectRAM also
includes dedicated routing resources to provide an efficient
interface with CLBs, block SelectRAM, and multipliers.
Read/Write Operations
The Virtex-II block SelectRAM read operation is fully syn-
chronous. An address is presented, and the read operation
is enabled by control signals WEA and WEB in addition to
ENA or ENB. Then, depending on clock polarity, a rising or
falling clock edge causes the stored data to be loaded into
output registers.
The write operation is also fully synchronous. Data and
address are presented, and the write operation is enabled
by control signals WEA or WEB in addition to ENA or ENB.
Then, again depending on the clock input mode, a rising or
falling clock edge causes the data to be loaded into the
memory cell addressed.
Table 19:
Dual-Port Mode Configurations
Port A
16K x 1
16K x 1
16K x 1
16K x 1
16K x 1
16K x 1
Port B
16K x 1
8K x 2
4K x 4
2K x 9
1K x 18
512 x 36
Port A
8K x 2
8K x 2
8K x 2
8K x 2
8K x 2
Port B
8K x 2
4K x 4
2K x 9
1K x 18
512 x 36
Port A
4K x 4
4K x 4
4K x 4
4K x 4
Port B
4K x 4
2K x 9
1K x 18
512 x 36
Port A
2K x 9
2K x 9
2K x 9
Port B
2K x 9
1K x 18
512 x 36
Port A
1K x 18
1K x 18
Port B
1K x 18
512 x 36
Port A
512 x 36
Port B
512 x 36
Figure 31:
18
Kbit
Block SelectRAM in Dual-Port Mode
DOPA
DOPB
DIPA
ADDRA
WEA
ENA
SSRA
CLKA
DIPB
ADDRB
WEB
ENB
SSRB
CLKB
18 Kbit Block SelectRAM
DS031_11_071602
DOB
DOA
DIA
DIB
Table 20:
18
Kbit
Block SelectRAM Port Aspect Ratio
Width
Depth
Address Bus
Data Bus
Parity Bus
1
16,384
ADDR[13:0]
DATA[0]
N/A
2
8,192
ADDR[12:0]
DATA[1:0]
N/A
4
4,096
ADDR[11:0]
DATA[3:0]
N/A
9
2,048
ADDR[10:0]
DATA[7:0]
Parity[0]
18
1,024
ADDR[9:0]
DATA[15:0]
Parity[1:0]
36
512
ADDR[8:0]
DATA[31:0]
Parity[3:0]
ds122_1_1.fm Page 28 Wednesday, January 7, 2004 9:15 PM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ2V6000-4CF1144N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4CG717M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4CG717N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
| XQ2V6000-4EF1152I | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Platform FPGAs |
| XQ2V6000-4FG456M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPro Virtex-II 1.5V Military QML Platform FPGAs |
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