參數(shù)資料
型號(hào): XQ2V1000-4BG575N
廠商: XILINX INC
元件分類: FPGA
英文描述: QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述: FPGA, 1280 CLBS, 1000000 GATES, 650 MHz, PBGA575
封裝: 1.27 MM PITCH, MS-034BAN-1, BGA-575
文件頁數(shù): 25/128頁
文件大?。?/td> 2738K
代理商: XQ2V1000-4BG575N
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
25
R
Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure 26
.
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions.
Figure 27
illustrates
LUT and MUXCY resources configured as a 16-input AND
gate.
Figure 26:
Horizontal Cascade Chain
MUXCY
4
MUXCY
4
Slice 1
ds031_64_110300
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 0
V
CC
LUT
LUT
MUXCY
4
MUXCY
4
Slice 3
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 2
V
CC
LUT
LUT
SOP
CLB
MUXCY
4
MUXCY
4
Slice 1
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 0
V
CC
LUT
LUT
MUXCY
4
MUXCY
4
Slice 3
ORCY
LUT
LUT
MUXCY
4
MUXCY
4
Slice 2
V
CC
LUT
LUT
CLB
Figure 27:
Wide-Input AND Gate (16 Inputs)
MUXCY
0
AND
4
16
MUXCY
0
4
“0”
1
1
“0”
0
1
“0”
MUXCY
4
Slice
OUT
OUT
Slice
LUT
DS031_41_110600
LUT
LUT
VCC
MUXCY
0
4
1
LUT
ds122_1_1.fm Page 25 Wednesday, January 7, 2004 9:15 PM
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