參數(shù)資料
型號： XQ2V1000-4BG575N
廠商： XILINX INC
元件分類： FPGA
英文描述： QPro Virtex-II 1.5V Military QML Platform FPGAs
中文描述： FPGA, 1280 CLBS, 1000000 GATES, 650 MHz, PBGA575
封裝： 1.27 MM PITCH, MS-034BAN-1, BGA-575
文件頁數(shù)： 7/128頁
文件大?。?/td> 2738K
代理商： XQ2V1000-4BG575N
QPro Virtex-II 1.5V Military QML Platform FPGAs
DS122 (v1.1) January 7, 2004
Product Specification
www.xilinx.com
1-800-255-7778
7
R
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as an input and/or an output for single-ended I/Os. Two
IOBs can be used as a differential pair. A differential pair is
always connected to the same switch matrix, as shown in
Figure 2
.
IOB blocks are designed for high-performance I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
CCINT
= 1.5V),
output driver supply voltage (V
CCO
) is dependent on the I/O
standard (see
Table 6
). An auxiliary supply voltage
(V
CCAUX
= 3.3 V) is required, regardless of the I/O stan-
dard used. For exact supply voltage absolute maximum rat-
ings, see
DC Input and Output Levels
.
Figure 2:
Virtex-II Input/Output Tile
IOB
PAD4
IOB
PAD3
Differential Pair
IOB
PAD2
IOB
PAD1
Differential Pair
Switch
Matrix
DS031_30_101600
Table 6:
Supported Single-Ended I/O Standards
I/O
Standard
Output
V
CCO
Input
V
CCO
Input
V
REF
Board
Termination
Voltage (V
TT
)
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
LVCMOS15
1.5
1.5
N/A
N/A
PCI33_3
3.3
3.3
N/A
N/A
PCI66_3
3.3
3.3
N/A
N/A
PCI-X
3.3
3.3
N/A
N/A
GTL
Note 1
Note 1
0.8
1.2
GTLP
Note 1
Note 1
1.0
1.5
HSTL_I
1.5
N/A
0.75
0.75
HSTL_II
1.5
N/A
0.75
0.75
HSTL_III
1.5
N/A
0.9
1.5
HSTL_IV
1.5
N/A
0.9
1.5
HSTL_I
1.8
N/A
0.9
0.9
HSTL_II
1.8
N/A
0.9
0.9
HSTL_III
1.8
N/A
1.1
1.8
HSTL_IV
1.8
N/A
1.1
1.8
SSTL2_I
2.5
N/A
1.25
1.25
SSTL2_II
2.5
N/A
1.25
1.25
SSTL3_I
3.3
N/A
1.5
1.5
SSTL3_II
3.3
N/A
1.5
1.5
AGP-2X/AGP
3.3
N/A
1.32
N/A
Notes:
1.
V
of GTL or GTLP should not be lower than the
termination voltage or the voltage seen at the I/O pad.
ds122_1_1.fm Page 7 Wednesday, January 7, 2004 9:15 PM
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