參數(shù)資料
型號： XPGA
廠商： Lattice Semiconductor Corporation
英文描述： The ispXPGA architecture
中文描述： 在ispXPGA架構(gòu)
文件頁數(shù)： 41/89頁
文件大?。?/td> 941K
代理商： XPGA
Lattice Semiconductor
ispXPGA Family Data Sheet
41
Signal Descriptions
1
Signal Name
Signal Type
Description
General Purpose
BK
y
_IO
x
1,2
GCLK
n
/I
n
7
Input/Output
General purpose I/O number x in I/O Bank y
Global clock/input
8
Input
GSR
Input
Global Set/Reset
NC
—
No Connect
GND
GND
Ground
V
CC
V
CCJ
V
CCO
y
V
REF
y
D
XN,
D
XP
VCC
Core logic power supply
VCC
IEEE 1149.1 TAP power supply
2
VCC
I/O Bank y power supply
2
Input
I/O Bank y reference voltage
Output
Temperature Sensing Diodes, provide a differential voltage, which
corresponds to the temperature of the device.
Test and Program/Con
fi
guration
TMS
Input
Test Mode Select
TCK
Input
Test Clock
TDI
Input
Test Data In
TDO
Output
Test Data Out
TOE
Input
Test Output Enable tri-states all I/O pins
CFG0
Input
Selects the SRAM memory con
fi
guration type (Peripheral or
E
2
CMOS Refresh)
Initiates download from E
2
CMOS or the peripheral port to SRAM
memory (active low)
PROGRAMb
Input
DONE
Bi-directional
Indicates when con
fi
guration is complete
INITb
Bi-directional
Indicates the device is ready for programming (active low)
READ
Input
Selects the READ operation when in sysCONFIG mode
CCLK
Input
sysCONFIG Con
fi
guration Clock
CSb
Input
sysCONFIG Chip Select (active low)
DATA[0:7]
sysCLOCK PLL
3
PLL_FBK
z
PLL_RST
z
CLK_OUT
z
PLL_LOCK
z
Bi-directional
sysCONFIG Peripheral Port Data I/O
Input
Optional external feedback
Input
Optional external M divider reset
Internal Signal Clock output (routable to any I/O)
Internal Signal Lock output (routable to any I/O)
GND
P
V
CCP
sysHSI Block
4, 5
HSI
m
A_SINP, HSI
m
B_SINP
HSI
m
A_SINN, HSI
m
B_SINN
HSI
m
A_SOUTP, HSI
m
B_SOUTP
HSI
m
A_SOUTN, HSI
m
B_SOUTN
HSI
m
A_LOSS, HSI
m
B_LOSS
HSI
m
A_SYDT, HSI
m
B_SYDT
HSI
m
A_RECCLK, HSI
m
B_RECCLK
HSI
m
A_CDRLOCK, HSI
m
B_CDRLOCK
GND
PLL Ground
VCC
PLL power supply
Input
P-side of differential serial data input
Input
N-side of differential serial data input
Output
P-side of differential serial data output
Output
N-side of differential serial data output
Internal Signal Detects loss of signal
Internal Signal Symbol alignment detect
Internal Signal Recovered clock
Internal Signal Indicates when the CDR circuit is locked
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XPGBWT-01-0000-00DC4 制造商:CREE 制造商全稱:Cree, Inc 功能描述:Cree?? XLamp?? XP Family LEDs
XPGBWT-01-0000-00DC5 功能描述:大功率LED - 白色 White, 107lm RoHS:否 制造商:Cree, Inc. 照明顏色:Cool White 顏色溫度:5000 K 光通量:280 lm 顯示角:125 deg 正向電流:700 mA 正向電壓:2.9 V 安裝風(fēng)格:SMD/SMT 系列:XMLBWW 封裝:Reel
XPGBWT-01-0000-00DC6 功能描述:大功率LED - 白色 White, 107lm RoHS:否 制造商:Cree, Inc. 照明顏色:Cool White 顏色溫度:5000 K 光通量:280 lm 顯示角:125 deg 正向電流:700 mA 正向電壓:2.9 V 安裝風(fēng)格:SMD/SMT 系列:XMLBWW 封裝:Reel
XPGBWT-01-0000-00DD4 制造商:CREE 制造商全稱:Cree, Inc 功能描述:Cree?? XLamp?? XP Family LEDs
XPGBWT-01-0000-00DD5 功能描述:大功率LED - 白色 White, 107lm RoHS:否 制造商:Cree, Inc. 照明顏色:Cool White 顏色溫度:5000 K 光通量:280 lm 顯示角:125 deg 正向電流:700 mA 正向電壓:2.9 V 安裝風(fēng)格:SMD/SMT 系列:XMLBWW 封裝:Reel
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