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參數(shù)資料
| 型號： | XC9572 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復雜可編程邏輯器件） |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 41K |
| 代理商： | XC9572 |
XAPP070 July, 1997 (Version 1.1)
1-9
1
Summary
This application Note discusses basic design considerations for in-system programming of multiple XC9500 devices in a
boundary-scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE
1149.1-compatible devices.
Xilinx Family
XC9500
Introduction
The XC9500 family performs both in-system programming
and IEEE 1149.1 boundary-scan (JTAG) testing via a sin-
gle 4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. Xilinx also provides the EZTag
TM
software that automatically programs and tests XC9500
devices from the standard test vector and device program-
ming files generated by most CPLD development tools.
XC9500 TAP Characteristics
The AC and DC characteristics of the XC9500 TAP are
described as follows.
TAP Timing
Figure 1
shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations. The timing for the
INPUT-I/O-CLK and I/O signals is relevant to boundary-
scan operations (such as EXTEST) that activate or strobe
the system pins.
Figure 1: Test Access Port Timing
Using In-System Programmability
in Boundary-Scan Systems
XAPP070 July, 1997 (Version 1.1)
Application Note
TCKMIN
TMSH
TMSS
TDIH
TDIS
TDOZX
TDOV
TINH
TINS
TIOV
TDOXZ
TCK
TMS
TDI
TDO
Input-I/O-CLK
I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC9572-10PC44 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9572 In-System Programmable CPLD |
| XC957210PC44C | 制造商:Xilinx 功能描述: |
| XC9572-10PC44C | 功能描述:IC CPLD 72 MCELL C-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC9572-10PC44C0166 | 制造商:Xilinx 功能描述: |
| XC9572-10PC44I | 功能描述:IC CPLD 72 MCELL I-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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