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參數(shù)資料
| 型號(hào)： | XC9572 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 6/6頁(yè) |
| 文件大?。?/td> | 41K |
| 代理商： | XC9572 |
Using In-System Programmability in Boundary-Scan Systems
1-14
XAPP070 July, 1997 (Version 1.1)
read from or written to the device internal program
memory. As long as the ISPEX instruction remains in
the instruction register the functional pins remain in
their lightly pulled-up high impedance state. Once the
ISPEX instruction is replaced with any other boundary-
scan instruction (except ISPEN), the device returns to
its initial power state with the pins configured to their
programmed states (input, output, or bidirectional) and
with the device flip-flops taking on their initial states.
The ISPEX operation takes approximately 100
microseconds to complete. If the ISPEX instruction is
held in the instruction register for longer than 100
microseconds, the ISPEX operation will not take effect
until the ISPEX instruction is displaced from the
instruction register.
In order to ensure safe operation, all INTEST,EXTEST, and
ISP operations involving the XC9500 parts should be
bracketed by ISPEN and ISPEX instructions.
The designer must also be careful to select an initial condi-
tion that is “system-safe” so that when the ISPEX instruc-
tion is released the XC9500 part in question will safely
resume operation with the rest of the system.
Basic Boundary-Scan Design Guidelines
The following guidelines will help ensure a successful
design.
Make certain that all parts in the boundary-scan chain
have 1149.1 compatible test access ports.
Use simple buffering for TCK/TMS signals, to simplify
test considerations for the boundary-scan TAP.
Do not invert TCK or TMS pathways, to guarantee
complete test software compatibility.
Group similar device families, and have a single level
converter interface between them, for TCK, TMS, TDI,
TDO, and system pins.
Check that the mission logic is safe from any possible
errors that might arise while the boundary-scan data is
being shifted through the boundary-scan chain. For
example, pay close attention to bus enable or chip
select signals that might be enabled simultaneously,
causing unexpected bus contention.
Provide the capability for the ATE to disable
conventional (non boundary-scan) IC’s whose run-time
node values might introduce conflicts with boundary-
scan logic values during test operations.
Verify that the entire system is held in a benign state
during boundary-scan test operations.
Verify that the set-up and hold times of TDI and TMS
with respect to TCK are met by the system.
Debugging Boundary-Scan Systems
The following guidelines and helpful information will help
isolate potential problems.
When traversing the IR states, the CAPTURE-IR value
specified in the BSDL file is always shifted out on TDO
at SHIFT-IR. This fact can be used to test boundary-
scan chain continuity.
After exit from Test-Logic-Reset, if the system
transitions directly to Shift-DR, the values shifted out on
TDO must be either the IDCODE (if implemented) or
the BYPASS register contents. If all logic 0’s are shifted
in at TDI, then the first incidence of a logic 1 on TDO
represents the first bit of an IDCODE. This fact can be
used for blind interrogation of the boundary-scan chain
and for further boundary-scan chain continuity checks.
When entering ISP mode via the ISPEN instruction, all
XC9500 function pins float to a weakly pulled-up high
impedance state. The pins can easily be tested for this
behavior.
When ISPEX is shifted out of the instruction register,
the XC9500 devices should take on their programmed
values with the functional pins acting immediately as
inputs or outputs, as programmed. The pins can easily
be tested for this behavior.
TDO assumes its defined value at the falling edge of
TCK.
When not in SHIFT-IR or SHIFT-DR, TDO exhibits high
impedance.
The last valid TDI bit clocks into the TAP with TMS high.
In BYPASS mode, TDO equals the applied TDI data
one TCK pulse earlier.
Conclusion
When designing ISP systems, common-sense rules related
to electronic system design and board layout should be
adhered to. In order to benefit from the synergies associ-
ated with the integration of test and programming opera-
tions the designer must consciously design with the entire
system life cycle in mind.
References
IEEE 1149.1-1990 Std Test Access Port and Boundary-
Scan Architecture
Colin Maunder and Rod Tulloss, The Test Access Port and
Boundary-Scan Architecture, ISBN: 0-8186-9070-4.
Kenneth P. Parker, The Boundary-Scan Handbook, ISBN:
0-7923-9270-1.
Harry Bleeker et al., Boundary-Scan Test - A Practical
Approach, ISBN: 0-792-9296-5.
Hideo Fujiwara, Logic Testing and Design for Testability,
ISBN: 0-262-06096-5.
M. Montrose, Printed Circuit Board Design Techniques,
ISBN: 0780311310.
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| XC9572-10PC44 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9572 In-System Programmable CPLD |
| XC957210PC44C | 制造商:Xilinx 功能描述: |
| XC9572-10PC44C | 功能描述:IC CPLD 72 MCELL C-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC9572-10PC44C0166 | 制造商:Xilinx 功能描述: |
| XC9572-10PC44I | 功能描述:IC CPLD 72 MCELL I-TEMP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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