參數資料
型號: XC6SLX100T-3FG900I
廠商: Xilinx Inc
文件頁數: 9/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 900FGGBGA
標準包裝: 27
系列: Spartan® 6 LXT
LAB/CLB數: 7911
邏輯元件/單元數: 101261
RAM 位總計: 4939776
輸入/輸出數: 498
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 900-BBGA
供應商設備封裝: 900-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
17
Endpoint Block for PCI Express Designs Switching Characteristics
The Endpoint block for PCI Express is available in the Spartan-6 LXT devices. Consult the Spartan-6 FPGA Integrated
Endpoint Block for PCI Express for further information.
Table 23: GTP Transceiver Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
TRXELECIDLE
Time for RXELECIDLE to respond to loss or restoration of data
75
ns
RXOOBVDPP
OOB detect threshold peak-to-peak
60
150
mV
RXSST
Receiver spread-spectrum tracking(1)
Modulated @ 33 KHz
–5000
0
ppm
RXRL
Run length (CID)
Internal AC capacitor bypassed
150
UI
RXPPMTOL
Data/REFCLK PPM offset
tolerance
CDR 2nd-order loop disabled
–200
200
ppm
CDR 2nd-order
loop enabled
PLL_RXDIVSEL_OUT = 1
–2000
2000
ppm
PLL_RXDIVSEL_OUT = 2
–2000
2000
ppm
PLL_RXDIVSEL_OUT = 4
–1000
1000
ppm
SJ Jitter Tolerance(2)
JT_SJ3.125
Sinusoidal Jitter(3)
3.125 Gb/s
0.4
UI
JT_SJ2.5
Sinusoidal Jitter(3)
2.5 Gb/s
0.4
UI
JT_SJ1.62
Sinusoidal Jitter(3)
1.62 Gb/s
0.5
UI
JT_SJ1.25
Sinusoidal Jitter(3)
1.25 Gb/s
0.5
UI
JT_SJ614
Sinusoidal Jitter(3)
614 Mb/s
0.5
UI
SJ Jitter Tolerance with Stressed Eye(2)(5)
JT_TJSE3.125
Total Jitter with stressed eye(4)
3.125 Gb/s
0.65
UI
JT_SJSE3.125
Sinusoidal Jitter with stressed eye
3.125 Gb/s
0.1
UI
JT_TJSE2.7
Total Jitter with stressed eye(4)
2.7 Gb/s
0.65
UI
JT_SJSE2.7
Sinusoidal Jitter with stressed eye
2.7 Gb/s
0.1
UI
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2.
All jitter values are based on a Bit Error Ratio of 1e–12.
3.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4.
Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ.
5.
Measured using PRBS7 data pattern.
Table 24: Maximum Performance for PCI Express Designs
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
FPCIEUSER
User clock maximum frequency
62.5
N/A
MHz
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