
DS312 (v4.1) July 19, 2013
Product Specification
9
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in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Design Documentation Available
The functionality of the Spartan-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
UG331: Spartan-3 Generation FPGA User Guide
Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
-
Distributed RAM
-
SRL16 Shift Registers
-
Carry and Arithmetic Logic
I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
UG332: Spartan-3 Generation Configuration User
Guide
Configuration Overview
-
Configuration Pins and Behavior
-
Bitstream Sizes
Detailed Descriptions by Mode
-
Master Serial Mode using Xilinx Platform
Flash PROM
-
Master SPI Mode using Commodity SPI Serial
Flash PROM
-
Master BPI Mode using Commodity Parallel
NOR Flash PROM
-
Slave Parallel (SelectMAP) using a Processor
-
Slave Serial using a Processor
-
JTAG Mode
ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Xilinx Alerts
Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
Sign Up for Alerts on Xilinx.com
Spartan-3E FPGA Starter Kit
For specific hardware examples, please see the Spartan-3E
FPGA Starter Kit board web page, which has links to
various design examples and the user guide.
Spartan-3E FPGA Starter Kit Board page
UG230: Spartan-3E FPGA Starter Kit User Guide
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Spartan-3E FPGA Family:
Functional Description
DS312 (v4.1) July 19, 2013
Product Specification