- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374985 > XC3S1000-4FG676I (XILINX INC) Spartan-3 FPGA Family : Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號： | XC3S1000-4FG676I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family : Complete Data Sheet |
| 中文描述： | FPGA, 1920 CLBS, 1000000 GATES, 630 MHz, PBGA676 |
| 封裝： | 27 X 27 MM, FBGA-676 |
| 文件頁數(shù)： | 8/192頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | XC3S1000-4FG676I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁
DS099-2 (v1.2) July 11, 2003
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
IOBs
IOB Overview
The Input/Output Block (IOB) provides a programmable,
bidirectional interface between an I/O pin and the FPGA’s
internal logic.
A simplified diagram of the IOB’s internal structure appears
in
Figure 1
. There are three main signal paths within the
IOB: the output path, input path, and 3-state path. Each
path has its own pair of storage elements that can act as
either registers or latches. For more information, see the
Storage Element Functions section. The three main signal
paths are as follows:
The input path carries data from the pad, which is
bonded to a package pin, through an optional
programmable delay element directly to the I line. After
the delay element, there are alternate routes through a
pair of storage elements to the IQ1 and IQ2 lines. The
IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s
internal logic. The delay element can be set to ensure a
hold time of zero.
The output path, starting with the O1 and O2 lines,
carries data from the FPGA’s internal logic through a
multiplexer and then a three-state driver to the IOB
pad. In addition to this direct path, the multiplexer
provides the option to insert a pair of storage elements.
The 3-state path determines when the output driver is
high impedance. The T1 and T2 lines carry data from
the FPGA’s internal logic through a multiplexer to the
output driver. In addition to this direct path, the
multiplexer provides the option to insert a pair of
storage elements.
All signal paths entering the IOB, including those
associated with the storage elements, have an inverter
option. Any inverter placed on these paths is
automatically absorbed into the IOB.
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting them to bits syn-
chronized on both the rising and the falling edge. The com-
bination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (FDDR).
See
Double-Data-Rate Transmission
, page 3
for more
information.
The signal paths associated with the storage element are
described in
Table 1
.
040
Spartan-3 1.2V FPGA Family:
Functional Description
DS099-2 (v1.2) July 11, 2003
0
0
Advance Product Specification
R
Table 1:
Storage Element Signal Description
Storage
Element
Signal
Description
Function
D
Data input
Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the
input is enabled, data passes directly to the output Q.
Q
Data output
The data on this output reflects the state of the storage element. For operation as a latch in
transparent mode, Q will mirror the data at D.
CK
Clock input
A signal’s active edge on this input with CE asserted, loads data into the storage element.
CE
Clock Enable input
When asserted, this input enables CK. If not connected, CE defaults to the asserted state.
SR
Set/Reset
Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.
REV
Reverse
Used together with SR. Forces storage element into the state opposite from what SR does.
相關PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-4FG900C | Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FG900I | Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FT256C | Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FT256I | Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4TQ144C | Spartan-3 FPGA Family: Complete Data Sheet |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-4FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S1000-4FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-4FGG320C | 功能描述:SPARTAN-3A FPGA 1M STD 320-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC3S1000-4FGG320I | 功能描述:IC SPARTAN-3A FPGA 1M 320-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC3S1000-4FGG456C | 功能描述:IC SPARTAN-3 FPGA 1M 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
發(fā)布緊急采購，3分鐘左右您將得到回復。