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參數(shù)資料
| 型號： | XC3195A-3PQ160C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 41/76頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 484 CLB'S 160-PQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標準包裝： | 24 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 484 |
| RAM 位總計： | 94984 |
| 輸入/輸出數(shù)： | 138 |
| 門數(shù)： | 7500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 其它名稱： | 122-1085 |
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R
XC3000 Series Field Programmable Gate Arrays
7-48
November 9, 1998 (Version 3.1)
XC3000L Absolute Maximum Ratings
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000L Global Buffer Switching Characteristics Guidelines
Notes: 1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.
Symbol
Description
Units
VCC
Supply voltage relative to GND
–0.5 to +7.0
V
VIN
Input voltage with respect to GND
–0.5 to VCC +0.5
V
VTS
Voltage applied to 3-state output
–0.5 to VCC +0.5
V
TSTG
Storage temperature (ambient)
–65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
TJ
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
Speed Grade
-8
Description
Symbol
Max
Units
Global and Alternate Clock Distribution1
Either: Normal IOB input pad through clock buffer
to any CLB or IOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TPID
TPIDC
9.0
7.0
ns
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T
↓ to L.L. active and valid with single pull-up resistor
T
↑ to L.L. High with single pull-up resistor
TIO
TON
TPUS
5.0
12.0
24.0
ns
BIDI
Bidirectional buffer delay
TBIDI
2.0
ns
Product Obsolete or Under Obsolescence
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