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參數(shù)資料
| 型號： | XC3195A-3PQ160C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 484 CLB'S 160-PQFP |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標準包裝： | 24 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 484 |
| RAM 位總計： | 94984 |
| 輸入/輸出數(shù)： | 138 |
| 門數(shù)： | 7500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-PQFP（28x28） |
| 其它名稱： | 122-1085 |
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R
November 9, 1998 (Version 3.1)
7-47
XC3000 Series Field Programmable Gate Arrays
7
XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000L Operating Conditions
Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to
restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclude operation at 5V. Operating
conditions are guaranteed in the 3.0 – 3.6 V VCC range.
XC3000L DC Characteristics Over Operating Conditions
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option. ICCO is in addition to ICCPD.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per VCC pin. The number of ground pins varies from the XC3020L to the XC3090L.
3. Not tested. Allows an undriven pin to float High. For any other purpose, use an external pull-up.
Symbol
Description
Min
Max
Units
VCC
Supply voltage relative to GND Commercial 0
°C to +85°C junction
3.0
3.6
V
VIH
High-level input voltage — TTL configuration
2.0
VCC+0.3
V
VIL
Low-level input voltage — TTL configuration
-0.3
0.8
V
TIN
Input signal transition time
250
ns
Symbol
Description
Min
Max
Units
VOH
High-level output voltage (@ IOH = –4.0 mA, VCC min)
2.40
V
VOL
Low-level output voltage (@ IOL = 4.0 mA, VCC min)
0.40
V
VOH
High-level output voltage (@ IOH = –4.0 mA, VCC min)
VCC -0.2
V
VOL
Low-level output voltage (@ IOL = 4.0 mA, VCC min)
0.2
V
VCCPD
Power-down supply voltage (PWRDWN must be Low)
2.30
V
ICCPD
Power-down supply current (VCC(MAX) @ TMAX)10
A
ICCO
Quiescent FPGA supply current in addition to ICCPD
1
Chip thresholds programmed as CMOS levels
20
A
IIL
Input Leakage Current
–10
+10
A
CIN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
IRIN
Pad pull-up (when selected) @ VIN = 0 V
3
0.01
0.17
mA
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
2.50
mA
Product Obsolete or Under Obsolescence
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