參數(shù)資料
型號(hào)： XC3190A-3PC84C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 67/76頁(yè)
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 9000GAT 84PLCC
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC3000A/L
LAB/CLB數(shù)： 320
RAM 位總計(jì)： 64160
輸入/輸出數(shù)： 70
門(mén)數(shù)： 6000
電源電壓： 4.25 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
產(chǎn)品目錄頁(yè)面： 601 (CN2011-ZH PDF)
其它名稱(chēng)： 122-1046
R
November 9, 1998 (Version 3.1)
7-9
XC3000 Series Field Programmable Gate Arrays
7
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The development system is used to
compile the configuration data which is to be loaded into
the internal configuration memory to define the operation
and interconnection of each block. User definition of CLBs
and their interconnecting networks may be done by auto-
matic translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the asyn-
chronous RD which, when enabled and High, is dominant
over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops’ present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
F
G
QX
QY
DIN
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
1
MUX
Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
-
five logic variable inputs A, B, C, D, and E
-
a direct data in DI
-
an enable clock EC
-
a clock (invertible) K
-
an asynchronous direct RESET RD
-
two outputs X and Y
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
ABC65DRXS CONN EDGECARD 130PS .100 DIP SLD
25LC040AX-I/ST IC EEPROM 4KBIT 10MHZ 8TSSOP
25LC040AT-I/ST IC EEPROM 4KBIT 10MHZ 8TSSOP
XC3S700A-5FGG400C IC SPARTAN-3A FPGA 700K 400FBGA
25LC040AT-I/MS IC EEPROM 4KBIT 10MHZ 8MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3190A-3PC84I 制造商:Xilinx 功能描述:
XC3190A-3PG175C 制造商:Xilinx 功能描述:
XC3190A-3PG175I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PP175C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-3PP175I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*