參數(shù)資料
型號: XC3042L-8VQ100I
廠商: Xilinx Inc
文件頁數(shù): 67/76頁
文件大?。?/td> 0K
描述: IC FPGA 3.3V I-TEMP 100-VQFP
產(chǎn)品變化通告: XC3000(L) Discontinuation 01/Feb/2003
標(biāo)準(zhǔn)包裝: 90
系列: XC3000A/L
LAB/CLB數(shù): 144
RAM 位總計: 30784
輸入/輸出數(shù): 82
門數(shù): 3000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
R
November 9, 1998 (Version 3.1)
7-9
XC3000 Series Field Programmable Gate Arrays
7
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The development system is used to
compile the configuration data which is to be loaded into
the internal configuration memory to define the operation
and interconnection of each block. User definition of CLBs
and their interconnecting networks may be done by auto-
matic translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the asyn-
chronous RD which, when enabled and High, is dominant
over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops’ present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
F
G
QX
QY
DIN
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
1
MUX
Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
-
five logic variable inputs A, B, C, D, and E
-
a direct data in DI
-
an enable clock EC
-
a clock (invertible) K
-
an asynchronous direct RESET RD
-
two outputs X and Y
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
AMM30DTKT-S288 CONN EDGECARD 60POS .156 EXTEND
RMC65DRXI-S734 CONN EDGECARD 130PS DIP .100 SLD
XC3042L-8VQ100C IC FPGA 3.3V C-TEMP 100-VQFP
ABB66DHAN-S621 CONN EDGECARD 132PS R/A .050 SLD
ABB66DHAD-S621 CONN EDGECARD 132PS R/A .050 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3042PC84BS70C 制造商:Xilinx 功能描述:
XC3042PQ100BKJ9721 制造商:XI 功能描述:3042PQ100BK XILINX S9I7B
XC3064 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families
XC3064100PC84C 制造商:XILINX 功能描述:NEW
XC3064-100PC84C 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 224 Cell, 84 Pin, Plastic, PLCC