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參數(shù)資料
| 型號(hào)： | XC3042L-8VQ100I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V I-TEMP 100-VQFP |
| 產(chǎn)品變化通告： | XC3000(L) Discontinuation 01/Feb/2003 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 144 |
| RAM 位總計(jì)： | 30784 |
| 輸入/輸出數(shù)： | 82 |
| 門數(shù)： | 3000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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R
November 9, 1998 (Version 3.1)
7-15
XC3000 Series Field Programmable Gate Arrays
7
Longlines
The Longlines bypass the switch matrices and are intended
primarily for signals that must travel a long distance, or
must have minimum skew among multiple destinations.
Longlines, shown in Figure 14, run vertically and horizon-
tally the height or width of the interconnect area. Each inter-
connection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
of switching matrices. In devices larger than the XC3020A
and XC3120A FPGAs, two vertical Longlines in each col-
umn are connectable half-length lines. On the XC3020A
and XC3120A FPGAs, only the outer Longlines are con-
nectable half-length lines.
Longlines can be driven by a logic block or IOB output on a
column-by-column basis. This capability provides a com-
mon low skew control or clock line within each column of
logic blocks. Interconnections of these Longlines are
shown in Figure 15. Isolation buffers are provided at each
input to a Longline and are enabled automatically by the
development system when a connection is made.
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.
Product Obsolete or Under Obsolescence
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