參數(shù)資料
型號: XC3042L-8VQ100I
廠商: Xilinx Inc
文件頁數(shù): 6/76頁
文件大?。?/td> 0K
描述: IC FPGA 3.3V I-TEMP 100-VQFP
產(chǎn)品變化通告: XC3000(L) Discontinuation 01/Feb/2003
標準包裝: 90
系列: XC3000A/L
LAB/CLB數(shù): 144
RAM 位總計: 30784
輸入/輸出數(shù): 82
門數(shù): 3000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 100-TQFP
供應商設備封裝: 100-VQFP(14x14)
R
XC3000 Series Field Programmable Gate Arrays
7-16
November 9, 1998 (Version 3.1)
Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area.
Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two
non-clock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.
VCC
DA
DB
DC
DN
VCC
Z = DA DB DC ... DN
X3036
(LOW)
Figure 16: 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.
D A
A
D B
B
D C
C
D N
N
D A A
+
=D B B
+ D C C
+
D N N
Z… +
X1741A
WEAK
KEEPER CIRCUIT
Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
Product Obsolete or Under Obsolescence
相關PDF資料
PDF描述
AMM30DTKT-S288 CONN EDGECARD 60POS .156 EXTEND
RMC65DRXI-S734 CONN EDGECARD 130PS DIP .100 SLD
XC3042L-8VQ100C IC FPGA 3.3V C-TEMP 100-VQFP
ABB66DHAN-S621 CONN EDGECARD 132PS R/A .050 SLD
ABB66DHAD-S621 CONN EDGECARD 132PS R/A .050 SLD
相關代理商/技術參數(shù)
參數(shù)描述
XC3042PC84BS70C 制造商:Xilinx 功能描述:
XC3042PQ100BKJ9721 制造商:XI 功能描述:3042PQ100BK XILINX S9I7B
XC3064 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families
XC3064100PC84C 制造商:XILINX 功能描述:NEW
XC3064-100PC84C 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 224 Cell, 84 Pin, Plastic, PLCC