- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4173 > XC3042A-7VQ100C (Xilinx Inc)IC FIELD PROG GATE ARRAY 100 PIN PDF資料下載
參數(shù)資料
| 型號： | XC3042A-7VQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 20/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIELD PROG GATE ARRAY 100 PIN |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 144 |
| RAM 位總計： | 30784 |
| 輸入/輸出數(shù)： | 82 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
R
November 9, 1998 (Version 3.1)
7-29
XC3000 Series Field Programmable Gate Arrays
7
Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.
The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again
when the byte-wide input buffer has transferred its informa-
tion into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
X5991
ADDRESS
BUS
DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC
CS0
...
RDY/BUSY
WS
RESET
...
OTHER
I/O PINS
D0–7
CCLK
DOUT
M2
HDC
LDC
FPGA
GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0
M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 k
*
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 27: Peripheral Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4003E-2PC84C | IC FPGA 84-PLCC |
| XC4005E-4PC84C | IC FPGA 196 CLB'S 84-PLCC |
| AMM36DRSN-S288 | CONN EDGECARD 72POS .156 EXTEND |
| AMM36DRSH-S288 | CONN EDGECARD 72POS .156 EXTEND |
| AMM36DRSD-S288 | CONN EDGECARD 72POS .156 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3042A-7VQ100I | 制造商:Xilinx 功能描述: |
| XC3042B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| XC3042L | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC3042L-8PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3042L-8PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
發(fā)布緊急采購，3分鐘左右您將得到回復。