- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4173 > XC3042A-7VQ100C (Xilinx Inc)IC FIELD PROG GATE ARRAY 100 PIN PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3042A-7VQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 16/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIELD PROG GATE ARRAY 100 PIN |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 144 |
| RAM 位總計(jì)： | 30784 |
| 輸入/輸出數(shù)： | 82 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
R
November 9, 1998 (Version 3.1)
7-25
XC3000 Series Field Programmable Gate Arrays
7
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
X5989_01
CE
GENERAL-
PURPOSE
USER I/O
PINS
M0
M1
PWRDWN
DOUT
M2
HDC
OTHER
I/O PINS
RESET
DIN
CCLK
DATA
CLK
+5 V
OE/RESET
XC3000
FPGA
DEVICE
D/P
SCP
CEO
CASCADED
SERIAL
MEMORY
LDC
INIT
XC17xx
RESET
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
DURING CONFIGURATION
THE 5 k
M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
(LOW RESETS THE XC17xx ADDRESS POINTER)
TO CCLK OF OPTIONAL
VCC
VPP
+5 V
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN
SERIES WITH M1
*
CE
DATA
CLK
OE/RESET
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
INIT
+5V
Figure 23: Master Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4003E-2PC84C | IC FPGA 84-PLCC |
| XC4005E-4PC84C | IC FPGA 196 CLB'S 84-PLCC |
| AMM36DRSN-S288 | CONN EDGECARD 72POS .156 EXTEND |
| AMM36DRSH-S288 | CONN EDGECARD 72POS .156 EXTEND |
| AMM36DRSD-S288 | CONN EDGECARD 72POS .156 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3042A-7VQ100I | 制造商:Xilinx 功能描述: |
| XC3042B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| XC3042L | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XC3042L-8PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3042L-8PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。