Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
43
08/01/03
3.0
Table 13: All Virtex-II devices and speed grades now Production.
Characteristics tables, based on values extracted from speedsfile version 1.116.
specified a capacitive load parameter.
Figure 1: Added note to figure regarding termination resistors.
10/14/03
3.1
Table 1: Changed TJ description from “Operating junction temperature” to “Maximum junction temperature”.
11713 with reference to XAPP689 regarding handling of simultaneously switching
outputs (SSO).
-
-
-
Revised and extended text describing output delay measurement procedure.
now available in these tables.
XC2V8000 is no longer offered in the -6 speed grade. The following tables containing
parameters or other references to this device/grade combination were corrected
Table 39: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
Footnote (2) to new Footnote (3).
03/29/04
3.2
-
For XC2V40, added Maximum quiescent supply current specifications.
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For all devices, updated Typical specifications for ICCINTQ and ICCAUXQ.
statement that power supplies can be turned on in any sequence.
diagrams as well as parameter specification tables formerly included in the Virtex-II (Global Clock Buffer S Input Setup/Hold to I1 and I2 Inputs).
parameters.
Recompiled for backward compatibility with Acrobat 4 and above.
06/24/04
3.3
Table 1: Added TSOL parameters for Pb-free package devices. 03/01/05
3.4
Characteristics tables, based on values extracted from speedsfile version 1.120.
Table 2: Corrected Footnote (1) to require connecting VBATT to VCCAUX or GND if battery is not used.
Table 3: Corrected "VREF current per bank" to "VREF current per pin." description of supply voltage ramp-on requirements. Added sentence to footnote (1)
indicating that if the stated requirements are violated, no damage to the device will
result, but configuration will probably fail.
Figure 3 and
Figure 4: Corrected to show DOUT transitions driven by falling edge of
CCLK.
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