Virtex-II Platform FPGAs: DC and Switching Characteristics
R
DS031-3 (v3.5) November 5, 2007
Module 3 of 4
Product Specification
23
Table 25: Pipelined Multiplier Switching Characteristics
Description
Symbol
Speed Grade
Units
-6
-5
-4
Setup and Hold Times Before/After Clock
Data Inputs
TMULIDCK/TMULCKID
3.00/ 0.00
3.45/ 0.00
3.89/ 0.00
ns, Max
Clock Enable
TMULIDCK_CE/TMULCKID_CE
0.72/ 0.00
0.80/ 0.00
0.86/ 0.00
ns, Max
Reset
TMULIDCK_RST/TMULCKID_RST
0.72/ 0.00
0.80/ 0.00
0.86/ 0.00
ns, Max
Clock to Output Pin
Clock to Pin 35
TMULTCK_P35
3.05
6.91
8.12
ns, Max
Clock to Pin 34
TMULTCK_P34
2.95
6.75
7.93
ns, Max
Clock to Pin 33
TMULTCK_P33
2.85
6.59
7.74
ns, Max
Clock to Pin 32
TMULTCK_P32
2.76
6.43
7.56
ns, Max
Clock to Pin 31
TMULTCK_P31
2.66
6.27
7.37
ns, Max
Clock to Pin 30
TMULTCK_P30
2.56
6.11
7.19
ns, Max
Clock to Pin 29
TMULTCK_P29
2.47
5.95
7.00
ns, Max
Clock to Pin 28
TMULTCK_P28
2.37
5.79
6.81
ns, Max
Clock to Pin 27
TMULTCK_P27
2.27
5.63
6.63
ns, Max
Clock to Pin 26
TMULTCK_P26
2.17
5.47
6.44
ns, Max
Clock to Pin 25
TMULTCK_P25
2.08
5.31
6.26
ns, Max
Clock to Pin 24
TMULTCK_P24
1.98
5.15
6.07
ns, Max
Clock to Pin 23
TMULTCK_P23
1.88
4.99
5.88
ns, Max
Clock to Pin 22
TMULTCK_P22
1.79
4.83
5.70
ns, Max
Clock to Pin 21
TMULTCK_P21
1.69
4.67
5.51
ns, Max
Clock to Pin 20
TMULTCK_P20
1.59
4.51
5.33
ns, Max
Clock to Pin 19
TMULTCK_P19
1.50
4.35
5.14
ns, Max
Clock to Pin 18
TMULTCK_P18
1.40
4.19
4.95
ns, Max
Clock to Pin 17
TMULTCK_P17
1.30
4.03
4.77
ns, Max
Clock to Pin 16
TMULTCK_P16
1.20
3.87
4.58
ns, Max
Clock to Pin 15
TMULTCK_P15
1.11
3.71
4.40
ns, Max
Clock to Pin 14
TMULTCK_P14
1.01
3.55
4.21
ns, Max
Clock to Pin 13
TMULTCK_P13
0.91
3.39
4.02
ns, Max
Clock to Pin 12
TMULTCK_P12
0.91
3.23
3.84
ns, Max
Clock to Pin 11
TMULTCK_P11
0.91
3.07
3.65
ns, Max
Clock to Pin 10
TMULTCK_P10
0.91
2.91
3.47
ns, Max
Clock to Pin 9
TMULTCK_P9
0.91
2.75
3.28
ns, Max
Clock to Pin 8
TMULTCK_P8
0.91
2.59
3.09
ns, Max
Clock to Pin 7
TMULTCK_P7
0.91
2.43
2.91
ns, Max
Clock to Pin 6
TMULTCK_P6
0.91
2.27
2.72
ns, Max
Clock to Pin 5
TMULTCK_P5
0.91
2.11
2.54
ns, Max
Clock to Pin 4
TMULTCK_P4
0.91
1.95
2.35
ns, Max
Clock to Pin 3
TMULTCK_P3
0.91
1.79
2.16
ns, Max
Clock to Pin 2
TMULTCK_P2
0.91
1.63
1.98
ns, Max
Clock to Pin 1
TMULTCK_P1
0.91
1.47
1.79
ns, Max
Clock to Pin 0
TMULTCK_P0
0.91
1.31
1.61
ns, Max