參數(shù)資料
型號: XC2S600E-6FG456Q
廠商: Xilinx Inc
文件頁數(shù): 4/108頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 3456
邏輯元件/單元數(shù): 15552
RAM 位總計: 294912
輸入/輸出數(shù): 329
門數(shù): 600000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
DS077-4 (v3.0) August 9, 2013
101
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, L64N_YY
2
J25
All
-
I/O, L64N_YY
I/O (D2), L64P_YY
2
J24
All
-
I/O (D2), L64P_YY
I/O (D1)
2
J23
-
I/O (D1)
I/O, VREF Bank 2,
L63N_YY
2
J22
All
I/O, VREF Bank 2,
L63N_YY
I/O, VREF Bank 2,
L63N_YY
I/O, L63P_YY
2
J21
All
-
I/O, L63P_YY
I/O, L62N_YY
2
J20
All
-
I/O, L62N_YY
I/O, L62P_YY
2
J19
All
-
I/O, L62P_YY
I/O
2
H22
-
I/O
I/O, L61N
2
H26
XC2S600E
-
I/O
I/O, L61N_Y
I/O, L61P
2
H25
XC2S600E
-
I/O, VREF Bank 2,
L61P_Y
I/O, L60N
2
H21
XC2S400E
-
I/O, L60N_Y
I/O, L60N
I/O, L60P
2
H20
XC2S400E
-
I/O, L60P_Y
I/O, L60P
I/O
2
G26
-
I/O
I/O, L59N_YY
2
G25
All
-
I/O, L59N_YY
I/O, L59P_YY
2
G24
All
-
I/O, L59P_YY
I/O
2
G23
-
I/O
I/O, L58N_YY
2
G22
All
-
I/O, L58N_YY
I/O, VREF Bank 2,
L58P_YY
2
G21
All
I/O, VREF Bank 2,
L58P_YY
I/O, VREF Bank 2,
L58P_YY
I/O
2
G20
-
I/O
I/O, L57N_YY
2
F26
All
-
I/O, L57N_YY
I/O, L57P_YY
2
F25
All
-
I/O, L57P_YY
I/O, L56N
2
F24
XC2S600E
-
I/O, L56N
I/O, L56N_Y
I/O, L56P
2
F23
XC2S600E
-
I/O, L56P
I/O, L56P_Y
I/O
2
F22
-
I/O
I/O, L55N
2
E26
XC2S600E
-
I/O, L55N
I/O, L55N_Y
I/O, VREF Bank 2,
L55P
2
E25
XC2S600E
All
I/O, VREF Bank 2,
L55P
I/O, VREF Bank 2,
L55P_Y
I/O, L54N
2
E23
XC2S400E
-
I/O, L54N_Y
I/O, L54N
I/O, L54P
2
E22
XC2S400E
-
I/O, L54P_Y
I/O, L54P
I/O, L53N_YY
2
F21
All
-
I/O, L53N_YY
I/O, L53P_YY
2
E21
All
-
I/O, L53P_YY
I/O, L52N
2
D26
XC2S600E
-
I/O
I/O, L52N_Y
I/O, L52P
2
D25
XC2S600E
-
I/O, L52P_Y
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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