參數(shù)資料
型號(hào): XC2S600E-6FG456Q
廠商: Xilinx Inc
文件頁(yè)數(shù): 3/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 3456
邏輯元件/單元數(shù): 15552
RAM 位總計(jì): 294912
輸入/輸出數(shù): 329
門(mén)數(shù): 600000
電源電壓: 1.71 V ~ 1.89 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
100
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O
3
N18
-
I/O
I/O (TRDY)
3
N24
-
I/O (TRDY)
I/O (IRDY), L75N_YY
2
N26
All
-
I/O (IRDY), L75N_YY
I/O, L75P_YY
2
N25
All
-
I/O, L75P_YY
I/O
2
N19
-
I/O
I/O, L74N
2
N23
XC2S600E
-
I/O, L74N_Y
I/O, L74P
2
N22
XC2S600E
-
I/O
I/O, L74P_Y
I/O
2
M23
-
I/O
I/O, L73N
2
N21
XC2S600E
-
I/O, L73N
I/O, L73N_Y
I/O, VREF Bank 2,
L73P
2
N20
XC2S600E
All
I/O, VREF Bank 2,
L73P
I/O, VREF Bank 2,
L73P_Y
I/O, L72N
2
M26
XC2S400E
-
I/O, L72N_Y
I/O, L72N
I/O, L72P
2
M25
XC2S400E
-
I/O, L72P_Y
I/O, L72P
I/O
2
M22
-
I/O
I/O, L71N_YY
2
M21
All
-
I/O, L71N_YY
I/O, L71P_YY
2
M20
All
-
I/O, L71P_YY
I/O
2
L26
-
I/O
I/O (D3), L70N_YY
2
M19
All
-
I/O (D3), L70N_YY
I/O, VREF Bank 2,
L70P_YY
2
M18
All
I/O, VREF Bank 2,
L70P_YY
I/O, VREF Bank 2,
L70P_YY
I/O, L69N
2
L25
XC2S600E
-
I/O, L69N
I/O, L69N_Y
I/O, L69P
2
L24
XC2S600E
-
I/O, L69P
I/O, L69P_Y
I/O
2
L22
-
I/O
I/O, L68N
2
L21
XC2S600E
-
I/O, L68N
I/O, L68N_Y
I/O, L68P
2
L20
XC2S600E
-
I/O, L68P
I/O, L68P_Y
I/O
2
L19
-
I/O
I/O, L67N
2
K26
XC2S600E
-
I/O, L67N
I/O, L67N_Y
I/O, L67P
2
K25
XC2S600E
-
I/O, L67P
I/O, L67P_Y
I/O, L66N
2
K24
-
I/O, L66N
I/O, L66P
2
K23
-
I/O
I/O, L66P
I/O
2
K22
-
I/O
I/O, L65N
2
K20
XC2S600E
-
I/O
I/O, L65N_Y
I/O, L65P
2
K19
XC2S600E
-
I/O
I/O, L65P_Y
I/O
2
J26
-
I/O
FG676 Pinouts (XC2S400E, XC2S600E) (Continued)
Pad Name
Pin
LVDS Async.
Output Option
VREF
Option
Device-Specific Pinouts
Function
Bank
XC2S400E
XC2S600E
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