參數(shù)資料
型號(hào)： XC2S200-5FGG256I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 50/99頁(yè)
文件大小： 0K
描述： IC SPARTAN-II FPGA 200K 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計(jì)： 57344
輸入/輸出數(shù)： 176
門數(shù)： 200000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
其它名稱： 122-1311
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
54
R
Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test
patterns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and
junction temperature). Values apply to all Spartan-II devices
unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)(1)
CTT
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
–0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note (2)
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2.
Tested according to the relevant specifications.
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
Symbol
Description
Device
Speed Grade
Units
All
-6
-5
Min
Max
TICKOFDLL
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, with DLL.
All
2.9
3.3
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
3.
DLL output jitter is already included in the timing calculation.
4.
For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Symbol
Description
Device
Speed Grade
Units
All
-6
-5
Min
Max
TICKOF
Global clock input to output delay
using output flip-flop for LVTTL,
12 mA, fast slew rate, without DLL.
XC2S15
4.5
5.4
ns
XC2S30
4.5
5.4
ns
XC2S50
4.5
5.4
ns
XC2S100
4.6
5.5
ns
XC2S150
4.6
5.5
ns
XC2S200
4.7
5.6
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables "Constants for Calculating TIOOP" and "Delay Measurement
3.
For data output with different standards, adjust delays with the values shown in "IOB Output Delay Adjustments for Different
Standards," page 59. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
相關(guān)PDF資料
PDF描述
RCB95DHAR CONN EDGECARD 190PS R/A .050 DIP
XC2S200-6FG256C IC FPGA 2.5V C-TEMP 256-FBGA
ASM40DRMI-S288 CONN EDGECARD 80POS .156 EXTEND
AMM25DTMS-S189 CONN EDGECARD 50POS R/A .156 SLD
XC2S200-5FG256I IC FPGA 2.5V I-TEMP 256-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S200-5FGG456C 功能描述:IC SPARTAN-II FPGA 200K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S200-5FGG456C4124 制造商:Xilinx 功能描述:
XC2S200-5FGG456I 功能描述:IC SPARTAN-II FPGA 200K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S200-5PQ208C 功能描述:IC FPGA 2.5V 1176 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S200-5PQ208I 功能描述:IC FPGA 2.5V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-II 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*