參數(shù)資料
型號： XC2S200-5FGG256I
廠商： Xilinx Inc
文件頁數(shù)： 48/99頁
文件大?。?/td> 0K
描述： IC SPARTAN-II FPGA 200K 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-II
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計： 57344
輸入/輸出數(shù)： 176
門數(shù)： 200000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
其它名稱： 122-1311
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
52
R
Recommended Operating Conditions
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Max
Units
TJ
Junction temperature(1)
Commercial
0
85
°C
Industrial
–40
100
°C
VCCINT
Supply voltage relative to GND(2,5)
Commercial
2.5 – 5%
2.5 + 5%
V
Industrial
2.5 – 5%
2.5 + 5%
V
VCCO
Supply voltage relative to GND(3,5)
Commercial
1.4
3.6
V
Industrial
1.4
3.6
V
TIN
Input signal transition time(4)
-
250
ns
Notes:
1.
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°C.
2.
Functional operation is guaranteed down to a minimum VCCINT of 2.25V (Nominal VCCINT – 10%). For every 50 mV reduction in
VCCINT below 2.375V (nominal VCCINT – 5%), all delay parameters increase by 3%.
3.
Minimum and maximum values for VCCO vary according to the I/O standard selected.
4.
Input and output measurement threshold is ~50% of VCCO. See "Delay Measurement Methodology," page 60 for specific levels.
5.
Supply voltages may be applied in any order desired.
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data Retention VCCINT voltage (below which configuration data
may be lost)
2.0
-
V
VDRIO
Data Retention VCCO voltage (below which configuration data may
be lost)
1.2
-
V
ICCINTQ
Quiescent VCCINT supply current(1)
XC2S15
Commercial
-
10
30
mA
Industrial
-
10
60
mA
XC2S30
Commercial
-
10
30
mA
Industrial
-
10
60
mA
XC2S50
Commercial
-
12
50
mA
Industrial
-
12
100
mA
XC2S100
Commercial
-
12
50
mA
Industrial
-
12
100
mA
XC2S150
Commercial
-
15
50
mA
Industrial
-
15
100
mA
XC2S200
Commercial
-
15
75
mA
Industrial
-
15
150
mA
ICCOQ
Quiescent VCCO supply current(1)
--
2
mA
IREF
VREF current per VREF pin
-
20
μA
IL
Input or output leakage current(2)
–10
-
+10
μA
CIN
Input capacitance (sample tested)
VQ, CS, TQ, PQ, FG
packages
--
8
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(3)
--
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(3)
--
0.15
mA
Notes:
1.
With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2.
The I/O leakage current specification applies only when the VCCINT and VCCO supply voltages have reached their respective
minimum Recommended Operating Conditions.
3.
Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
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