參數(shù)資料
型號(hào)： XC2S150-6PQ208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 51/99頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 2.5V C-TEMP 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-II
LAB/CLB數(shù)： 864
邏輯元件/單元數(shù)： 3888
RAM 位總計(jì)： 49152
輸入/輸出數(shù)： 140
門(mén)數(shù)： 150000
電源電壓： 2.375 V ~ 2.625 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Spartan-II FPGA Family: DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
Module 3 of 4
Product Specification
55
R
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSDLL / TPHDLL
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
with DLL
All
1.7 / 0
1.9 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
4.
A zero hold time listing indicates no hold time or a negative hold time.
5.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
Symbol
Description
Device
Speed Grade
Units
-6
-5
Min
TPSFD / TPHFD
Input setup and hold time relative
to global clock input signal for
LVTTL standard, no delay, IFF,(1)
without DLL
XC2S15
2.2 / 0
2.7 / 0
ns
XC2S30
2.2 / 0
2.7 / 0
ns
XC2S50
2.2 / 0
2.7 / 0
ns
XC2S100
2.3 / 0
2.8 / 0
ns
XC2S150
2.4 / 0
2.9 / 0
ns
XC2S200
2.4 / 0
3.0 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
A zero hold time listing indicates no hold time or a negative hold time.
4.
For data input with different standards, adjust the setup time delay by the values shown in "IOB Input Delay Adjustments for Different
Standards," page 57. For a global clock input with standards other than LVTTL, adjust delays with values from the "I/O Standard
相關(guān)PDF資料
PDF描述
XC2S150-5PQ208I IC FPGA 2.5V I-TEMP 208-PQFP
HMM44DSAI CONN EDGECARD 88POS R/A .156 SLD
AMC28DRYI-S93 CONN EDGECARD 56POS DIP .100 SLD
XC3S400A-5FGG320C IC SPARTAN-3A FPGA 400K 320FBGA
XC3S400A-5FG320C IC SPARTAN-3A FPGA 400K 320FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S150-6PQ208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S150-6PQG208C 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 208PQFP - Trays
XC2S150-6PQG208I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II FPGA Family
XC2S150-6TQ144C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S150-6TQ144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*