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    參數(shù)資料
    

    


    


    
型號(hào)：
XC2S150-6PQ208C

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
27/99頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA 2.5V C-TEMP 208-PQFP

    

    
標(biāo)準(zhǔn)包裝：
24

    

    
系列：
Spartan®-II

    

    
LAB/CLB數(shù)：
864
    		

    

    
邏輯元件/單元數(shù)：
3888
    		

    

    
RAM 位總計(jì)：
49152
    		

    

    
輸入/輸出數(shù)：
140
    		

    

    
門數(shù)：
150000
    		

    

    
電源電壓：
2.375 V ~ 2.625 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
208-BFQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
208-PQFP（28x28）
    		

    

    

    

	
    
    
    

    
    
	
    Spartan-II FPGA Family: Functional Description
    DS001-2 (v2.8) June 13, 2008
    Module 2 of 4
    Product Specification
    33
    R
    Port Signals
    Each block RAM port operates independently of the others
    while accessing the same set of 4096 memory cells.
    Table 12 describes the depth and width aspect ratios for the
    block RAM memory.
    Clock—CLK[A|B]
    Each port is fully synchronous with independent clock pins.
    All port input pins have setup time referenced to the port
    CLK pin. The data output bus has a clock-to-out time
    referenced to the CLK pin.
    Enable—EN[A|B]
    The enable pin affects the read, write and reset functionality
    of the port. Ports with an inactive enable pin keep the output
    pins in the previous state and do not write data to the
    memory cells.
    Write Enable—WE[A|B]
    Activating the write enable pin allows the port to write to the
    memory cells. When active, the contents of the data input
    bus are written to the RAM at the address pointed to by the
    address bus, and the new data also reflects on the data out
    bus. When inactive, a read operation occurs and the
    contents of the memory cells referenced by the address bus
    reflect on the data out bus.
    Reset—RST[A|B]
    The reset pin forces the data output bus latches to zero
    synchronously. This does not affect the memory cells of the
    RAM and does not disturb a write operation on the other
    port.
    Address Bus—ADDR[A|B]<#:0>
    The address bus selects the memory cells for read or write.
    The width of the port determines the required width of this
    bus as shown in Table 12.
    Data In Bus—DI[A|B]<#:0>
    The data in bus provides the new data value to be written
    into the RAM. This bus and the port have the same width,
    as shown in Table 12.
    Data Output Bus—DO[A|B]<#:0>
    The data out bus reflects the contents of the memory cells
    referenced by the address bus at the last active clock edge.
    During a write operation, the data out bus reflects the data
    in bus. The width of this bus equals the width of the port.
    The allowed widths appear in Table 12.
    Inverting Control Pins
    The four control pins (CLK, EN, WE and RST) for each port
    have independent inversion control as a configuration
    option.
    Address Mapping
    Each port accesses the same set of 4096 memory cells
    using an addressing scheme dependent on the width of the
    port. The physical RAM location addressed for a particular
    width are described in the following formula (of interest only
    when the two ports use different aspect ratios).
    Start = ([ADDRport + 1] * Widthport) – 1
    End = ADDRport * Widthport
    Table 13 shows low order address mapping for each port
    width.
    RAMB4_S4
    RAMB4_S4_S4
    RAMB4_S4_S8
    RAMB4_S4_S16
    4N/A
    4
    8
    16
    RAMB4_S8
    RAMB4_S8_S8
    RAMB4_S8_S16
    8N/A
    8
    16
    RAMB4_S16
    RAMB4_S16_S16
    16
    N/A
    16
    Table 12: Block RAM Port Aspect Ratios
    Width
    Depth
    ADDR Bus
    Data Bus
    1
    4096
    ADDR<11:0>
    DATA<0>
    2
    2048
    ADDR<10:0>
    DATA<1:0>
    4
    1024
    ADDR<9:0>
    DATA<3:0>
    8
    512
    ADDR<8:0>
    DATA<7:0>
    16
    256
    ADDR<7:0>
    DATA<15:0>
    Table 11: Available Library Primitives
    Primitive
    Port A Width
    Port B Width
    Table 13: Port Address Mapping
    Port
    Widt
    h
    Port
    Addresses
    1
    4095...
    1
    5
    1
    4
    1
    3
    1
    2
    1
    0
    9
    0
    8
    0
    7
    0
    6
    0
    5
    0
    4
    0
    3
    0
    2
    0
    1
    0
    2
    2047...
    07
    06
    05
    04
    03
    02
    01
    00
    4
    1023...
    03
    02
    01
    00
    8
    511...
    01
    00
    16
    255...
    00
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC2S150-6PQ208I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family

    

    
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