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參數(shù)資料
| 型號： | XC2S150-6PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 23/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2.5V C-TEMP 208-PQFP |
| 標準包裝： | 24 |
| 系列： | Spartan®-II |
| LAB/CLB數(shù)： | 864 |
| 邏輯元件/單元數(shù)： | 3888 |
| RAM 位總計： | 49152 |
| 輸入/輸出數(shù)： | 140 |
| 門數(shù)： | 150000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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Spartan-II FPGA Family: Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
Module 1 of 4
Product Specification
3
R
General Overview
The Spartan-II family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited
reprogramming cycles are possible with this approach.
Stored values in these cells determine logic functions and
interconnections implemented in the FPGA. Configuration
data can be read from an external serial PROM (master
serial mode), or written into the FPGA in slave serial, slave
parallel, or Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume
applications where the versatility of a fast programmable
solution adds benefits. Spartan-II FPGAs are ideal for
shortening product development cycles while offering a
cost-effective solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and
semiconductor technology. Spartan-II devices provide
system clock rates up to 200 MHz. In addition to the
conventional benefits of high-volume programmable logic
solutions, Spartan-II FPGAs also offer on-chip synchronous
single-port and dual-port RAM (block and distributed form),
DLL clock drivers, programmable set and reset on all
flip-flops, fast carry logic, and many other features.
Figure 1: Basic Spartan-II Family FPGA Block Diagram
XC2S15
DLL
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
I/O LOGIC
CLBs
DS001_01_091800
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| XC2S150-5PQ208I | IC FPGA 2.5V I-TEMP 208-PQFP |
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| AMC28DRYI-S93 | CONN EDGECARD 56POS DIP .100 SLD |
| XC3S400A-5FGG320C | IC SPARTAN-3A FPGA 400K 320FBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S150-6PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-6PQG208C | 制造商:Xilinx 功能描述:FPGA SPARTAN-II 150K GATES 3888 CELLS 263MHZ 2.5V 208PQFP - Trays |
| XC2S150-6PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S150-6TQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| XC2S150-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
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