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參數(shù)資料
| 型號： | XC161CS-32F |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| 中文描述： | 16位單片機(jī)與C166SV2核心 |
| 文件頁數(shù)： | 59/84頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | XC161CS-32F |
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XC161-32
Derivatives
Electrical Parameters
Data Sheet
57
V1.0, 2004-11
Configuration pull-
down current
12)
I
CPDL
I
CPDH
I
LHI
10)
–
120
–
10
–
-10
μ
A
μ
A
μ
A
V
IN
=
V
ILmax
V
IN
=
V
IHmin
V
OUT
= 0.5
×
V
DDP
V
OUT
= 0.45 V
11)
Level inactive hold
current
13)
Level active hold
current
13)
XTAL1, XTAL3 input
current
Pin capacitance
14)
(digital inputs/outputs)
10)
I
LHA
11)
-100
–
μ
A
I
IL
CC
–
±
20
μ
A
0 V <
V
IN
<
V
DDI
C
IO
CC
–
10
pF
–
1) Keeping signal levels within the limits specified in this table, ensures operation without overload conditions.
For signal levels outside these specifications, also refer to the specification of the overload current
I
OV
.
2) If XTAL3 is driven by a crystal, reaching an amplitude (peak to peak) of 0.25
×
V
DDI
is sufficient.
3) This parameter is tested for P2, P3, P4, P6, P7, P9.
4) The maximum deliverable output current of a port driver depends on the selected output driver mode, see
Table 12
,
Current Limits for Port Output Drivers
. The limit for pin groups must be respected.
5) As a rule, with decreasing output current the output levels approach the respective supply level (
V
OL
→
V
SS
,
V
OH
→
V
DDP
). However, only the levels for nominal output currents are guaranteed.
6) This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
7) An additional error current (
I
INJ
) will flow if an overload current flows through an adjacent pin. Please refer to
the definition of the overload coupling factor
K
OV
.
8) The driver of P3.15 is designed for faster switching, because this pin can deliver the reference clock for the
bus interface (CLKOUT). The maximum leakage current for P3.15 is, therefore, increased to 1
μ
A.
9) This specification is valid during Reset for configuration on RD, WR, EA, PORT0.
The pull-ups on RD and WR (WRL/WRH) are also active during bus hold.
10)The maximum current may be drawn while the respective signal line remains inactive.
11)The minimum current must be drawn to drive the respective signal line active.
12)This specification is valid during Reset for configuration on ALE.
The pull-down on ALE is also active during bus hold.
13)This specification is valid during Reset for pins P6.4-0, which can act as CS outputs.
The pull-ups on CS outputs are also active during bus hold.
The pull-up on pin HLDA is active when arbitration is enabled and the EBC operates in slave mode.
14)Not subject to production test - verified by design/characterization.
Table 11
DC Characteristics
(Operating Conditions apply)
1)
(cont’d)
Parameter
Symbol
Limit Values
Unit Test Condition
Min.
Max.
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