參數資料
| 型號： | XA3S700A-4FGG484Q |
| 廠商： | Xilinx Inc |
| 文件頁數： | 11/57頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA SPARTAN-3A 700K 484-FBGA |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 1 |
| 系列： | Spartan®-3A XA |
| LAB/CLB數： | 1472 |
| 邏輯元件/單元數： | 13248 |
| RAM 位總計： | 368640 |
| 輸入/輸出數： | 372 |
| 門數： | 700000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 484-BBGA |
| 供應商設備封裝： | 484-FBGA |
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XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
19
Pin-to-Pin Setup and Hold Times
Input Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade: -4
Units
Min
Setup Times
TPSDCM
When writing to the Input Flip-Flop (IFF), the
time from the setup of data at the Input pin
to the active transition at a Global Clock pin.
The DCM is in use. No Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
XA3S200A
2.84
ns
XA3S400A
2.68
ns
XA3S700A
2.57
ns
XA3S1400A
2.17
ns
TPSFD
When writing to IFF, the time from the setup
of data at the Input pin to an active transition
at the Global Clock pin. The DCM is not in
use. The Input Delay is progr ammed.
LVCMOS25(2),
IFD_DELAY_VALUE = 5,
without DCM
XA3S200A
2.76
ns
XA3S400A
2.60
ns
XA3S700A
2.63
ns
XA3S1400A
2.41
ns
Hold Times
TPHDCM
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
XA3S200A
–0.52
ns
XA3S400A
–0.29
ns
XA3S700A
–0.12
ns
XA3S1400A
0.00
ns
TPHFD
When writing to IFF, the time from the active
transition at the Global Clock pin to the point
when data must be held at the Input pin. The
DCM is not in use. The Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 5,
without DCM
XA3S200A
–0.56
ns
XA3S400A
–0.42
ns
XA3S700A
–0.75
ns
XA3S1400A
–0.69
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4.
DCM output jitter is included in all measurements.
Table 20: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Speed Grade: -4
Units
Min
Setup Times
TIOPICK
Time from the setup of data at the
Input pin to the active transition at
the ICLK input of the Input
Flip-Flop (IFF). No Input Delay is
programmed.
LVCMOS25(2)
0
XA3S200A
1.81
ns
XA3S400A
1.51
ns
XA3S700A
1.51
ns
XA3S1400A
1.74
ns
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| XA3SD1800A-4CSG484I | 功能描述:SPARTAN-3ADSP FPGA 1800K 484CSBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan®-3A DSP XA 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數:4080 邏輯元件/單元數:52224 RAM 位總計:4866048 輸入/輸出數:480 門數:- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，FCBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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