參數(shù)資料
型號(hào): XA3S500E-4PQG208Q
廠商: Xilinx Inc
文件頁(yè)數(shù): 22/37頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3E 500K 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: Spartan®-3E XA
LAB/CLB數(shù): 1164
邏輯元件/單元數(shù): 10476
RAM 位總計(jì): 368640
輸入/輸出數(shù): 158
門數(shù): 500000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
DS635 (v2.0) September 9, 2009
Product Specification
29
R
Configuration and JTAG Timing
Table 33: Power-On Timing and the Beginning of Configuration
Symbol
Description
Device
-4 Speed Grade
Units
Min
Max
TPOR(2)
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
XA3S100E
-
5
ms
XA3S250E
-
5
ms
XA3S500E
-
5
ms
XA3S1200E
-
5
ms
XA3S1600E
-
7
ms
TPROG
The width of the low-going pulse on the PROG_B pin
All
0.5
-
μs
TPL(2)
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
XA3S100E
-0.5
ms
XA3S250E
-0.5
ms
XA3S500E
-1
ms
XA3S1200E
-2
ms
XA3S1600E
-2
ms
TINIT
Minimum Low pulse width on INIT_B output
All
250
-ns
TICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
0.5
4.0
μs
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2.
Power-on reset and the clearing of configuration memory occurs during this period.
3.
This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.
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