FN8201.0 April 18, 2005 or analog control register is essentially a write to a static RAM. The response of the wiper to this action
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� X9448WV24I-2.7
寤犲晢锛� Intersil
鏂囦欢闋佹暩(sh霉)锛� 15/19闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DUAL PROG COMP 10K 24TSSOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 75
绯诲垪锛� XDCP™
鎺ョ墖锛� 64
闆婚樆锛堟瓙濮嗭級锛� 10k
闆昏矾鏁�(sh霉)锛� 2
婧害绯绘暩(sh霉)锛� 妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C
瀛樺劜鍣ㄩ鍨嬶細 闈炴槗澶�
鎺ュ彛锛� I²C锛堣ō(sh猫)鍌欎綅鍧€锛�
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宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 24-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 24-TSSOP
鍖呰锛� 绠′欢
5
FN8201.0
April 18, 2005
or analog control register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed tSTPWV. A transfer from the Wiper
Counter Register current wiper position to a data reg-
ister is a write to nonvolatile memory and takes a mini-
mum of tWR to complete. The transfer can occur
between one of the two potentiometers or one of the
two voltage comparators and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between both of the potentiometers and volt-
age comparators and one of their associated registers.
Four instructions require a three-byte sequence to com-
plete. The basic sequence is illustrated in Figure 4.
These instructions transfer data between the host and
the X9448; either between the host and one of the data
registers or directly between the host and the wiper
counter and analog control registers. These instructions
are: read wiper counter register or analog control regis-
ter, read the current wiper position of the selected pot or
the comparator control bits, Write wiper counter register
or analog control register, i.e. change current wiper
position of the selected pot or control the voltage com-
parator; read data register, read the contents of the
selected nonvolatile register; write data register, write a
new value to the selected data register. The bit struc-
tures of the instructions are shown in Figure 6.
The increment/decrement command is different from
the other commands. Once the command is issued
and the X9448 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the VL terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
Figure 3. Two-Byte Command Sequence
Figure 4. Three-Byte Command Sequence
Figure 5. Increment/Decrement Command Sequence
S
T
A
R
T
0101
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1
R0
P1 P0
A
C
K
SCL
SDA
S
T
O
P
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
P1 P0 R1 R0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D5 D4 D3 D2
D1 D0
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
P1 P0 R1 R0
A
C
K
SCL
SDA
S
T
O
P
X
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
X9448
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
X9448YP24 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Mixed Signal with 2-Wire Interface
X9448YP24-2.7 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Mixed Signal with 2-Wire Interface
X9448YP24I 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Mixed Signal with 2-Wire Interface
X9448YP24I-2.7 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Mixed Signal with 2-Wire Interface
X9448YS24 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Mixed Signal with 2-Wire Interface