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參數(shù)資料
| 型號(hào)： | X76F641XG-2.0 |
| 廠商： | IC MICROSYSTEMS Sdn. Bhd. |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | X76F641XG-2.0 |
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X76F641
9
Figure 9. Reset Password
Figure 10. Reset Device
Reset Password
COMMAND
Reset
Password
7
Reset
Password
0
S
SDA
Wait t
WC
OR
Repeated
ACK POLLING
COMMAND
S
ACK Polling
Command
S
If ACK, then
Device reset
7025 FM 14
Reset Device
COMMAND
Reset
Password
7
Reset
Password
0
S
SDA
Wait t
WC
OR
Repeated
ACK POLLING
COMMAND
S
ACK Polling
Command
S
If ACK, then
Device reset
7025 FM 15
RESPONSE TO RESET (DEFAULT = 19 41 AA 55)
The ISO Response to reset is controlled by the RST and
CLK pins. When RST is pulsed high during a clock pulse,
the device will output 32 bits of data, one bit per clock,
and it resets to the standby state. This conforms to the
ISO standard for “synchronous response to resThe part
must not be in a write cycle for the response to reset to
occur.
After initiating a nonvolatile write cycle the RST pin must
not be pulsed until the nonvolatile write cycle is complete.
If not, the ISO response will not be activated. If the RST
is pulsed HIGH and the CLK is within the RST pulse
(meet the t
NOL
spec.) in the middle of an ISO transaction,
it will output the 32 bit sequence again (starting at bit 0).
Otherwise, this aborts the ISO operation and the part
returns to standby state. If the RST is pulsed HIGH and the
CLK is outside the RST pulse (in the middle of an
ISO transaction), this aborts the ISO operation and the
part returns to standby state.
If there is power interrupted during the Response to
Reset, the response to reset will be aborted and the part
will return to the standby state. A Response to Reset is not
available during a nonvolatile write cycle.
S
A
A
A
A
S
A
N
S
S
A
A
A
A
S
A
N
S
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