- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372533 > X40237 Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器) PDF資料下載
參數(shù)資料
| 型號(hào)： | X40237 |
| 英文描述： | Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器) |
| 中文描述： | 綜合系統(tǒng)管理IC三電壓監(jiān)測器，葡萄牙，2千比特的EEPROM內(nèi)存，單/雙副處長（帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器） |
| 文件頁數(shù)： | 19/39頁 |
| 文件大?。?/td> | 215K |
| 代理商： | X40237 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
X4023x
– Preliminary Information
Characteristics subject to change without notice.
19 of 39
REV 1.0.4 7/12/01
www.xicor.com
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1
and BL0 bits written to the CR register. It is possible to
lock the regions of EEPROM memory shown in the
table below:
If the user attempts to perform a write operation on a
protected region of EEPROM memory, the operation is
aborted without changing any data in the array.
When the Block Lock bits of the CR register are set to
something other than BL1=0 and BL0=0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
The factory default setting for these bits are BL1 = 0,
BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X4023x is active (HIGH), then all nonvolatile write oper-
ations to both the EEPROM memory and DCPs are
inhibited, irrespective of the Block Lock bit settings
(See "WP: Write Protection Pin").
PUP1, PUP0: Power On Reset bits – (Nonvolatile)
Applying voltage to V
circuit which holds RESET output HIGH, until the sup-
CC
activates the Power On Reset
ply voltage stabilizes above the V
period of time, t
PURST
TRIP1
threshold for a
(See Figure 30).
The Power On Reset bits, PUP1 and PUP0 of the CR
register determine the t
PURST
On Reset circuitry (See "VOLTAGE MONITORING
FUNCTIONS"). These bits of the CR register are non-
volatile, and therefore power up to the last written state.
delay time of the Power
The nominal Power On Reset delay time can be
selected from the following table, by writing the appro-
priate bits to the CR register:
The default for these bits are PUP1 = 0, PUP0 = 1.
V2FS, V3FS: Voltage Monitor Status Bits (Volatile)
Bits V2FS and V3FS of the CR register are latched, vol-
atile flag bits which indicate the status of the Voltage
Monitor reset output pins V2FAIL and V3FAIL.
At power up the VxFS (x=2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appro-
priate value to the CR register. To provide consistency
between the VxFAIL and V
the V
xFS
bits can only be set to a “1” when the corre-
sponding VxFAIL output is HIGH.
xFS
however, the status of
Once the VxFS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding V
xFAIL
output becomes LOW.
BL1
BL0
Protected Addresses
(Size)
Partition of array
locked
0
0
None (Default)
None (Default)
0
1
C0
h
- FF
- FF
h
(64 bytes
)
Upper 1/4
1
0
80
h
h
(128 bytes
)
Upper 1/2
1
1
00
h
- FF
h
(256 bytes)
All
BL1
BL0
DCP Write Operation Permissible
0
0
YES (Default)
0
1
NO
1
0
NO
1
1
NO
PUP1
PUP0
Power on Reset delay (t
PURESET
)
0
0
50ms
0
1
100ms (Default)
1
0
200ms
1
1
300ms
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
C
K
1
1
1
1
1
1
1
1
A
C
K
SCL
SDA
S
T
O
P
A
C
K
CS7 CS6CS5 CS4 CS3 CS2CS1 CS0
SLAVE ADDRESS BYTE
ADDRESS BYTE
CR REGISTER DATA IN
Figure 18. CR Register Write Command Sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X40239 | Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器) |
| x40410(中文) | 4kbit EEPROM Dual Voltage Monitor with Integrated CPU Supervisor(4K位EEPROM 雙電壓監(jiān)測的CPU監(jiān)控器) |
| X40420(中文) | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40421(中文) | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40430(中文) | Dual Voltage Monitor with Intergrated CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40237S16I-A | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40237S16I-AT1 | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40237S16I-B | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40237S16I-BT1 | 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40239 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。