參數(shù)資料
型號: X40237
英文描述: Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
中文描述: 綜合系統(tǒng)管理IC三電壓監(jiān)測器,葡萄牙,2千比特的EEPROM內(nèi)存,單/雙副處長(帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
文件頁數(shù): 13/39頁
文件大小: 215K
代理商: X40237
X4023x
– Preliminary Information
Characteristics subject to change without notice.
13 of 39
REV 1.0.4 7/12/01
www.xicor.com
the associated NVM register remains unchanged.
Therefore, when V
CC
to the device is powered down
then back up, the “wiper position” reverts to that last
written to the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x=0,1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular
DCP, the Write Enable Latch (WEL) bit of the CR Reg-
ister must first be set (See “BL1, BL0: Block Lock pro-
tection bits - (Nonvolatile)” on page 18.)
The Slave Address Byte 10101110 specifies that a
Write to a DCP is to be conducted. An ACKNOWL-
EDGE is returned by the X4023x after the Slave
Address, if it has been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to
be written, while the WT bit determines if the Write is to
be volatile or nonvolatile. If the Instruction Byte format
is valid, another ACKNOWLEDGE is then returned by
the X4023x.
Following the Instruction Byte, a Data Byte is issued to
the X4023x over SDA. The Data Byte contents is
latched into the WCR of the DCP on the first rising
edge of the clock signal, after the LSB of the Data Byte
(D0) has been issued on SDA (See Figure 34).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON)
of the DCP. The maximum value for the Data Byte
depends upon which DCP is being addressed (see fol-
lowing table).
Using a Data Byte larger than the values specified
above results in the “wiper terminal” being set to the
highest tap position. The “wiper position” does NOT
roll-over to the lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data Byte
maps one to one to the “wiper position” of the DCP
“wiper terminal”. Therefore, the Data Byte 00001111
(15
10
) corresponds to setting the “wiper terminal” to
tap position 15. Similarly, the Data Byte 00011100
(28
10
) corresponds to setting the “wiper terminal” to
tap position 28. The mapping of the Data Byte to “wiper
position” data for DCP1 (100 Tap), is shown in
“APPENDIX 1” . An example of a simple C language
function which “translates” between the tap position
(decimal) and the Data Byte (binary) for DCP1, is given
in “APPENDIX 2” .
It should be noted that all writes to any DCP of the
X4023x are random in nature. Therefore, the Data Byte
of consecutive write operations to any DCP can differ
by an arbitrary number of bits. Also, setting the bits
P1=1, P0=1 is a reserved sequence, and will result in
no ACKNOWLEDGE after sending an Instruction Byte
on SDA.
The factory default setting of all “wiper position” set-
tings is with 00h stored in the NVM of the DCPs. This
corresponds to having the “wiper terminal”
R
WX
(x=0,1,2) at the “l(fā)owest” tap position, Therefore, the
resistance between
R
WX
and
R
LX
is a minimum
(essentially only the Wiper Resistance,
R
W
).
S
T
A
R
T
1
0
1
0
1
1
1
0
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
S
T
O
P
A
C
K
D7
D6
D5
D4
D3
D2
D1
D0
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
Figure 9.
DCP Write Command Sequence
P1- P0
DCPx
# Taps
Max. Data Byte
0
0
x=0
64
3Fh
0
1
x=1
100
Refer to Appendix 1
1
0
x=2
256
FFh
1
1
Reserved
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