參數(shù)資料
型號: X40237
英文描述: Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
中文描述: 綜合系統(tǒng)管理IC三電壓監(jiān)測器,葡萄牙,2千比特的EEPROM內(nèi)存,單/雙副處長(帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
文件頁數(shù): 11/39頁
文件大?。?/td> 215K
代理商: X40237
X4023x
– Preliminary Information
Characteristics subject to change without notice.
11 of 39
REV 1.0.4 7/12/01
www.xicor.com
At both ends of each array and between each resistor
segment there is a CMOS switch connected between
the resistor array and the wiper (R
w
x
) output. Within
each individual array, only one switch may be turned on
at any one time. These switches are controlled by the
Wiper Counter Register (WCR) (See Figure 6). The
WCR is a volatile register.
On power up of the X4023x, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap posi-
tion to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X4023x
might experience in a Hot Pluggable situation. On
power up, V
CC
applied to the X4023x may exhibit some
amount of ringing, before it settles to the required
value.
The device is designed such that the wiper terminal
(R
Wx
) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
V
CC
exceeds V
TRIP1
for a time exceeding t
PURST
(the
Power On Reset time, set in the CR Register - See
“CONTROL AND STATUS REGISTER” on page 18.).
Therefore, if
t
trans
is defined as the time taken for V
CC
to settle above V
TRIP1
(Figure 7): then the desired
wiper terminal position is recalled by (a maximum)
time:
t
trans
+
t
PURST
. It should be noted that
t
trans
is
determined by system hot plug conditions.
DCP Operations
In total there are three operations that can be per-
formed on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
ACK
returned
Issue Slave Address
Byte (Read or Write)
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue STOP
Issue START
NO
YES
High Voltage Cycle
complete. Continue
command sequence
Issue STOP
NO
Continue normal
Read or Write
command sequence
PROCEED
YES
Figure 5.
Acknowledge Polling Sequence
DECODER
RESISTOR
ARRAY
R
Hx
FET
SWITCHES
R
Wx
0
1
2
N
WIPER
COUNTER
REGISTER
(WCR)
NON
MEMORY
(NVM)
VOLATILE
“WIPER”
Figure 6.
DCP Internal Structure
DCP
Initial Values Before Recall
R
0
(64 TAP)
R
1
(100 TAP)
R
2
(256 TAP)
V
H
(TAP = 63)
V
L
(TAP = 0)
V
H
(TAP = 255)
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X40239 Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
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X40239 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP