參數(shù)資料
型號(hào)： X40235
英文描述： Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
中文描述： 綜合系統(tǒng)管理IC三電壓監(jiān)測(cè)器，葡萄牙，2千比特的EEPROM內(nèi)存，單/雙副處長(zhǎng)（帶2K的EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器）
文件頁(yè)數(shù)： 8/39頁(yè)
文件大?。?/td> 215K
代理商： X40235
X4023x
– Preliminary Information
Characteristics subject to change without notice.
8 of 39
REV 1.0.4 7/12/01
www.xicor.com
DETAILED DEVICE DESCRIPTION
The X4023x combines One or Two Xicor Digitally Con-
trolled Potentiometer (XDCP) devices, V
CC
power on
reset control, V
CC
low voltage reset control, two sup-
plementary voltage monitors with independent outputs,
and integrated EEPROM with Block Lock protection,
in one package. The integrated functionality of the
X4023x lowers system cost, increases reliability, and
reduces board space requirements.
DCPs allow for the “set-and-forget” adjustment during
production test or in-system updating via the industry
standard 2-wire interface.
Applying voltage to V
CC
activates the Power On Reset
circuit which sets the RESET output HIGH, until the
supply voltage stabilizes for a period of time (50-300
msec selectable via software). The RESET output then
goes LOW. The Low Voltage Reset circuit sets the
RESET output HIGH when V
CC
falls below the mini-
mum V
CC
trip point. RESET remains HIGH until V
CC
returns to proper operating level and stabilizes for a
period of time (t
PURST)
. A Manual Reset (MR) input
allows the user to externally activate the RESET out-
put.
Two supplementary Voltage Monitor circuits, V2MON
and V3MON, continuously compare their inputs to indi-
vidual trip voltages (independent on-chip voltage refer-
ences factory set and user programmable). When an
input voltage exceeds it’s associated trip level, the cor-
responding output (V3FAIL, V2FAIL) goes HIGH. When
the input voltage becomes lower than it’s associated
trip level, the corresponding output is driven LOW. A
corresponding binary representation of the two monitor
circuit outputs (V2FAIL and V3FAIL) are also stored in
latched, volatile (CR) register bits. The status of these
two monitor outputs can be read out via the 2-wire
serial port. The bits will remain SET, even after the
alarm condition is removed, allowing advanced recov-
ery algorithms to be implemented.
Xicor’s unique circuits allow for all internal trip voltages
to be individually programmed with high accuracy,
either by Xicor at final test or by the user during their
production process. Some distributors offer V
TRIP
reprogramming as a value added service. This gives
the designer great flexibility in changing system param-
eters, either at the time of manufacture, or in the field.
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s Block Lock
TM
protection.
This memory may be used to store module manufac-
turing data, serial numbers, or various other system
parameters. The EEPROM array is internally organized
as x 8, and utilizes Xicor’s proprietary Direct Write
TM
cells providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
The device features a 2-Wire interface.
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and
receive operations. The X4023x operates as a slave in
all applications.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW (see Figure 1). SDA state changes while
SCL is HIGH are reserved for indicating START and
STOP conditions. See Figure 1. On power up of the
X4023x, the SDA pin is in the input mode.
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1.
Valid Data Changes on the SDA Bus
相關(guān)PDF資料
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X40237 Integrated System Management IC Triple Voltage Monitors, POR, 2 kbit EEPROM Memory, and Single/Dual DCP(帶2K EEPROM和單/雙數(shù)字電位器的三路電壓監(jiān)控器)
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參數(shù)描述
X40235S16I-A 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-AT1 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-B 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40235S16I-BT1 功能描述:IC VOLTAGE MON TRPL EE 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40237 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP
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