- 您現在的位置：買賣IC網 > PDF目錄371189 > X1203S8 IC-SMD-RTC WITH EEPROM PDF資料下載
參數資料
| 型號： | X1203S8 |
| 英文描述： | IC-SMD-RTC WITH EEPROM |
| 中文描述： | 集成電路表面貼裝與EEPROM的時鐘 |
| 文件頁數： | 9/20頁 |
| 文件大?。?/td> | 88K |
| 代理商： | X1203S8 |
X1203
Characteristics subject to change without notice.
9 of 20
Figure 6. Byte Write Sequence
Figure 7. Page Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
CCR Address 1
Data
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
CCR Address 0
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
A
C
K
A
C
K
CCR Address 0
S
t
a
r
t
S
t
o
p
Slave
Address
CCR Address 1
Data (n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data (1)
A
C
K
(1
≤
n
≤
8)
1
1
1
1
0
1
1
0 0 0 0 0 0 0 0
After the receipt of each byte, the X1203 responds with
an acknowledge, and the address is internally incre-
mented by one. When the counter reaches the end of
the page, it “rolls over” and goes back to the first
address on the same page. If the master supplies
more than 8 bytes of data, then the previously loaded
data is over written by the new data, one byte at a time.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
non volatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. Refer to Figure 7 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The disabling of the inputs during non volatile write
cycles can be used to take advantage of the typical
5mS write cycle time. Once the stop condition is issued
to indicate the end of the master’s byte load operation,
the device initiates the internal non volatile write cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the non volatile write cycle
then no ACK will be returned. If the device has com-
pleted the write operation, an ACK will be returned and
the host can then proceed with the read or write opera-
tion. Refer to the flow chart in Figure 8.
相關PDF資料 |
PDF描述 |
|---|---|
| X1203S8I | 30V Single N-Channel HEXFET Power MOSFET in a D-Pak package; Similar to IRFR3303 with Lead Free Packaging |
| X1203V8 | Real-Time Clock |
| X1228S14I-4.5A | RTC Module With CPU Supervisor |
| X1228V14I-4.5A | RTC Module With CPU Supervisor |
| X1228 | RTC Module With CPU Supervisor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| X1203S8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| X1203V8 | 制造商:Intersil Corporation 功能描述: |
| X-120-499 | 制造商:Brady Corporation 功能描述:VIAL SIDE/TOP COMBO-B499 .50X1X.375DIA |
| X1205 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar |
| X1205S8 | 功能描述:IC RTC/CALENDAR 2-WIRE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數據格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN EP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。