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參數(shù)資料
| 型號： | WV3HG32M72EEU665D4MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.45 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 173K |
| 代理商： | WV3HG32M72EEU665D4MG |
WV3HG32M72EEU-D4
January 2006
Rev. 0
ADVANCED
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC OPERATING CONDITIONS (continued)
≤TCASE ≤ +85°C; VCC = +1.8V ± 0.1V
Self
Refresh
AC Characteristics
Symbol
806
665
534
403
Units
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
REFRESH to Active or Refresh to Refresh command
interval
tRFC (256MB)
TBD
127.5
70,000
75
70,000
75
70,000
ns
Average periodic refresh interval
tREFI
TBD
7.8
s
Exit self refresh to non-READ command
tXSNR
TBD
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tISXR
TBD
tIS
ps
ODT
ODT turn-on delay
tAOND
TBD
22222
tCK
ODT turn-on
tAOND
TBD
tAC (MIN)
tAC (MAX +
700)
tAC (MIN)
tAC (MAX +
1,000)
tAC (MIN)
tAC (MAX +
1,000)
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC (MIN)
tAC (MAX +
600)
tAC (MIN)
tAC (MAX +
600)
tAC (MIN)
tAC (MAX +
600)
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC (MIN) +
2,000
tAC (MAX) +
1,000
tAC (MIN) +
2,000
tAC (MAX) +
1,000
tAC (MIN) +
2,000
tAC (MAX) +
1,000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC (MIN) +
2,000
tAC (MAX) +
1,000
tAC (MIN) +
2,000
tAC (MAX) +
1,000
tAC (MIN) +
2,000
tAC (MAX) +
1,000
ps
ODT to power-down entry latency
tANPD
TBD
333
tCK
ODT power-down exit latency
tAXPD
TBD
888
tCK
Power
Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
TBD
222
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
TBD
7 - AL
6 - AL
Exit precharge power-down to any non-READ command.
tXP
TBD
222
tCK
CKE minimum high/low time
tCKE
TBD
333
tCK
Note:
AC specication is based on SAMSUNG components. Other DRAM manufactures specications may be different.
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