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參數(shù)資料
| 型號(hào)： | WV3HG32M72EEU665D4MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.45 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 173K |
| 代理商： | WV3HG32M72EEU665D4MG |
WV3HG32M72EEU-D4
January 2006
Rev. 0
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
AC OPERATING CONDITIONS (continued)
≤TCASE ≤ +85°C; VCC = +1.8V ± 0.1V
Command
and
Address
AC Characteristics
Symbol
806
665
534
403
Units
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Address and control input pulse width for each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tISb
TBD
200
250
ps
Address and control input hold time
tIHb
TBD
275
375
475
CACS# to CACS# command delay
tCCD
TBD
22
2
tCK
ACTIVE to ACTIVE (same bank) command
tRC
TBD
55
60
65
ns
ACTIVE bank a to ACTIVE bank command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
ACTIVE to PRECHARGE command
tRAS
TBD
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge time
tDAL
TBD
tWR + tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
10
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
ns
PRECHARGE ALL command period
tRPA
TBD
tRP + tCK
tRP +
tCK
tRP +
tCK
ns
LOAD MODE command cycle time
tMRD
TBD
22
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
4.375
ns
Note:
AC specication is based on SAMSUNG components. Other DRAM manufactures specication may be different.
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