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參數(shù)資料
| 型號(hào)： | WEDPF2M64B-70BM3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 64 FLASH 3.3V PROM MODULE, 70 ns, PBGA119 |
| 封裝： | STACKED TSOP, BGA-119 |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 317K |
| 代理商： | WEDPF2M64B-70BM3 |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPF2M64-XBX3
FIG 13: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS
NOTES:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
Addresses
555 for Program
2AA for Erase
PA
tWC
WE
OE
CS
Data
tAS
tAH
tCPH
tWS
In
Progress
Complete
RESET
tDH
tDS
PD for Program
30 for Sector Erase
10 for Chip Erase
WEDPF2M64FIG13.EPS
PA for Program
SA for Sector Erase
555 for Chip Erase
Data
Polling
tWH
tGHEL
tWHWH1 OR 2
tBUSY
tHR
A0 for Program
55 for Erase
RB/RY
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