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參數(shù)資料
| 型號： | WE512K8-300CQA |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 512K X 8 EEPROM 5V MODULE, 300 ns, CDIP32 |
| 封裝： | HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 678K |
| 代理商： | WE512K8-300CQA |
WE512K8, WE256K8,
WE128K8-XCX
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
March 2007
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Figure 5 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
places the selected data byte on I/O0 through I/O7 after the
access time. The output of the memory is placed in a high
impedance state shortly after either the OE# line or CS# line
is returned to a high level.
AC READ CHARACTERISTICS (See Figure 5)
FOR WE512K8-XCX
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
trc
150
200
250
300
ns
Address Access Time
tacc
150
200
250
300
ns
Chip Select Access Time
tacs
150
200
250
300
ns
Output Hold from Address Change, OE# or CS#
toh
0000
ns
Output Enable to Output Valid
toe
85
100
125
ns
Chip Select or Output Enable to High Z Output
tdf
70
ns
FOR WE256K8-XCX and WE128K8-XCX
Parameter
Symbol
-150
-200
Unit
Min
Max
Min
Max
Read Cycle Time
trc
150
200
ns
Address Access Time
tacc
150
200
ns
Chip Select Access Time
tacs
150
200
ns
Output Hold from Address Change, OE# or CS#
toh
0
ns
Output Enable to Output Valid
toe
85
ns
Chip Select or Output Enable to High Z Output
tdf
70
ns
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
NOTE:
OE# may be delayed up to tACS-tOE after the falling edge of CS# without impact on tOE
or by tACC-tOE after an address change without impact on tACC.
READ
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